Synopsys Collaborates with Samsung Foundry to Develop DesignWare IP for Samsung 8-nm FinFET Process
Collaboration Provides Lowest-Risk Path to Silicon Success for Designers Developing SoCs in Samsung Processes Targeting Low-Power, High-Performance Applications
MOUNTAIN VIEW, Calif. -- March 8, 2018 --Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with Samsung Foundry to develop DesignWare® Foundation IP for Samsung's 8-nanometer (nm) Low Power Plus (8LPP) FinFET process technology. Providing DesignWare Logic Library and Embedded Memory IP on Samsung's latest process technology enables designers to take advantage of a reduction in power and area compared to Samsung's 10LPP process. The DesignWare Foundation IP will be developed to meet strict automotive-grade requirements, enabling designers to accelerate ISO 26262 and AEC-Q100 qualifications of their advanced driver assistance system (ADAS) and infotainment system-on-chips (SoCs). The DesignWare Logic Library and Embedded Memory IP will be available from Synopsys through the Foundry-Sponsored IP Program for the Samsung 8LPP process, enabling qualified customers to license the IP at no cost. The collaboration extends Synopsys' and Samsung's long history of working together to provide silicon-proven IP that helps designers meet their performance, power, and area requirements for a wide range of applications including mobile, automotive, and cloud computing.
"Samsung's collaboration with Synopsys over the last decade has enabled first-pass silicon success for billions of ICs in mobile and consumer applications," said Jongwook Kye, vice president of Design Enablement at Samsung Electronics. "As designs get more complex and migrate to smaller FinFET processes, Samsung's advanced 8LPP process with Synopsys' high-quality Foundation IP solutions will enable designers to differentiate their products for mobile, cryptocurrency and network/server applications, accelerate project schedules, and quickly ramp into volume production."
"Samsung and Synopsys share a long and successful history of providing designers with silicon-proven DesignWare IP on Samsung's processes ranging from 180 to 10 nanometer," said John Koeter, vice president of marketing for IP at Synopsys. "As the leading provider of physical IP with more than 100 test chip tapeouts on FinFET processes, Synopsys continues to make significant investments in developing IP to help designers take advantage of Samsung's latest process technologies, reduce risk and speed development of their SoCs."
Availability
DesignWare Logic Libraries and Embedded Memories for Samsung 8LPP are scheduled to be available in Q2 2018 at no cost to qualified licensees from Synopsys as part of the Foundry-Sponsored IP Program. Contact Synopsys for details on automotive-grade application support.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot IP
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys Delivers Higher Productivity and Quality for Advanced-Node 5G/6G SoCs on Samsung Foundry's Low-Power Process
- Samsung Foundry Certifies Synopsys Design Compiler NXT for 5/4nm FinFET Process Technologies
- Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process
- Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process
- Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC N7+ FinFET Process
Breaking News
- Equal1 advances scalable quantum computing with CMOS-compatible silicon spin qubit technology
- New Breakthroughs in China's RISC-V Chip Industry
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Intel Announces Strategic Investment by Silver Lake in Altera
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- AMD Achieves First TSMC N2 Product Silicon Milestone
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |