Corigine adds certified USB IP to SiFive's Growing DesignShare Economy to Accelerate Adoption of RISC-V

Range of USB IP solutions now available through DesignShare program designed to speed adoption of open source-based semiconductors

SAN MATEO, Calif. – March 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the addition of Corigine, a fabless semiconductor and IP company, to the DesignShare economy.

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USB 3.1 SuperSpeed+ (Gen2) PC Host Controller (USB-IF Certified) USB 3.1 SuperSpeed PC Host Controller (USB-IF Certified) USB 3.1 SuperSpeed Device Controller (USB-IF Certified)

Through this partnership, Corigine will make available its USB-IF certified USB 3.1 Gen 1 and Gen 2, and USB 2.0 device, PC host and dual-role controller IP solutions for SiFive’s Freedom platform as part of the DesignShare initiative.

Adoption of USB 3.1 Gen 2 is being driven by a broad range of applications, most many involving large file sizes or high-resolution video streams, that demand high bandwidth. System designers will benefit from Corigine’s optimized, next-generation USB architecture that delivers the smallest size, lowest power and maximum configuration. The reduced gate count will contribute to less memory requirement, which lowers overall system cost. The logic sharing between device and host will further reduce the area consumption, providing the most economical and efficient solution for customers.

“The cost to bring a chip from design to realization continues to increase. This severely limits innovation to a handful of companies and inventors that have the money and time to come up with new designs,” said Shafy Eltoukhy, VP of operations and head of DesignShare at SiFive. “Companies like Corigine recognize the opportunities DesignShare provides, and we’re excited to bring new alternatives for aspiring inventors.”

The DesignShare ecosystem provides any company, inventor or maker the ability to harness the power of custom silicon with little to no upfront risk. Companies like SiFive, Corigine and other DesignShare partners have developed efficient, pre-integrated solutions to enable users to develop their prototypes without the significant investment in upfront engineering costs typically required to bring a custom chip design to realization.

“The innovative approach of DesignShare is encouraging more silicon designs in an area where we see tremendous growth,” said Ali Khan, VP of business and product development, Corigine. “Corigine is committed to providing differentiating IP solutions to benefit more customers, and we believe that participating in DesignShare will help lower the design barriers and add value to the semiconductor ecosystem.”

Since DesignShare launched last year, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to reconfigurable FPGA. For more information on DesignShare, visit www.sifive.com/designshare.

About SiFive

SiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit www.sifive.com.

About Corigine

Corigine, Inc. is a fabless semiconductor and IP company headquartered in Santa Clara, Calif., with design centers in Shanghai, Nanjing and Hong Kong, China. Corigine delivers intellectual property (IP) solutions for high-speed I/O as well as semiconductor products for connectivity, storage and machine learning applications targeted at cloud, automotive and smart city markets. Corigine’s seasoned IP experts from top fabless semiconductor companies leverage an advanced architecture to deliver innovations for emerging applications for reduced power, area and memory utilization while ensuring maximum performance and configurability.

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