Path to 2nm May Not Be Worth It
Diminishing returns may evaporate at 5nm
Rick Merritt, EETimes
3/23/2018 01:01 AM EDT
SANTA CLARA, Calif. — Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure they will be able to squeeze commercial advantages from them even at 5nm.
The increasing complexity and cost of making ever smaller chips is leading to diminishing returns. Data rates are peaking at 3 GHz for mobile processors, and power and area gains will narrow at 7nm, said a Qualcomm engineer in a panel at a Synopsys user group event here.
Speed gains of 16 percent at 10nm may dry up at 7nm due to resistance in metal lines. Power savings will shrink from 30 percent at 10nm to 10-25 percent at 7nm, and area shrinks may decline from 37 percent at 10nm to 20-30 percent at 7nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.
For decades, the electronics industry followed a roadmap codified by Moore’s Law of doubling the number of transistors on a chip roughly every two years. The result was a fast pace of ever smaller, faster, cheaper products from PCs to smartphones.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards