eSilicon deep learning ASIC in production qualification
Chip employs TSMC CoWoS® technology to integrate SoC and HBM2
SAN JOSE, Calif. — May 1, 2018 — eSilicon, an independent provider of FinFET-class ASICs, custom IP, and advanced 2.5D packaging solutions, today announced that the deep learning ASIC that taped out last September has moved to production qualification.
The ASIC includes custom pseudo two-port memories designed by eSilicon, TSMC’s Chip on Wafer on Substrate (CoWoS) technology, 28G SerDes, and four second-generation high-bandwidth memory stacks (HBM2). eSilicon’s end-to-end 2.5D/HBM2 solution includes 2.5D ecosystem management, silicon-proven HBM2 PHY, ASIC physical design, 2.5D package design, manufacturing, assembly and test.
The CoWoS interposer is over 1,000 square mm and contains over 170,000 microbumps. The design has successfully passed test bring-up and is in final qualification. Four-high and eight-high HBM stack versions are in qualification. This design is in the industry vanguard of ASICs targeting deep learning applications.
The 2.5D/HBM2 single package implementation gives the ASIC many advantages:
- Orders of magnitude higher total bandwidth in a much smaller board footprint
- Highly parallel connections to memory stacks inside the package for fast access
- Significant reduction in power consumption
“This design greatly expands the possibilities for deep learning, and we are delighted to enter final qualification,” said Ajay Lalwani, vice president, global manufacturing operations at eSilicon. “TSMC’s 2.5D CoWoS packaging technology has been a key differentiator for this advanced design.”
About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
|
Related News
- eSilicon Announces Production Qualification of 5G Infrastructure ASIC
- eSilicon tapes out deep learning ASIC
- Expedera Announces First Production Shipments of Its Deep Learning Accelerator IP in a Consumer Device
- ASIC Design Services Adds Core Deep Learning IP to SiFive DesignShare Program
- eSilicon revolutionizes machine learning ASIC platform (MLAP) market
Breaking News
- GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
- QuickLogic Announces $6.575 Million Contract Award for its Strategic Radiation Hardened Program
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
Most Popular
- GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- QuickLogic Announces $6.575 Million Contract Award for its Strategic Radiation Hardened Program
- Micon Global and Silvaco Announce New Partnership
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
E-mail This Article | Printer-Friendly Page |