Arasan Announces Industries First MIPI I3C Master IP Core compliant to the I3C HCI Specifications v1.0
Arasan Chip Systems announces the immediate availability of its MIPI I3C HCI Master IP Core for Mobile and Automobile SoC Designs
May 9, 2018 -- San Jose, CA -- Arasan Chip Systems announces the immediate availability of its MIPI I3C Host Controller Interface (“I3C HCI”) Master IP core compliant to the just released MIPI I3C HCI Specification Ver 1.0. The new I3C HCI specification standardizes the interface to enable building of common software drivers to enable easy access to the I3C HCI v1.0 Compliant Host Controllers.
Related |
I3C Host Controller |
As part of its Total IP Solution for I3C, Arasan also includes a Linux software stack compatible with our I3C HCI Master IP Core, an I3C Hardware Development Kit which enables prototyping and compliance testing of I3C products and the I3C Slave IP Core.
“Arasan has been a contributing member of the MIPI Association since 2005 and is happy to be the first out with the I3C HCI IP which builds upon our leadership in MIPI.” said Dr. Sam Beal, Marketing Director at Arasan. “Standardization of the interface will ease the adoption of I3C and promote compliance.”
Arasan’s I3C HCI Master IP Core is fully configurable across multiple parameters through simple scripts based on the customer’s specifications making it suitable for a variety of Sensor applications. Arasan’s I3C IP has been validated at the RTL level with 3’rd party VIP and System Level at I3C interoperability sessions conducted by the MIPI Association. Licensees can be assured of an I3C compliant IP from Arasan
Our I3C IP has also been seamlessly integrated with our MIPI CSI Tx and CSI Rx IP cores along with our Universal C-PHY / D-PHY Combo PHY IP to enable camera sensor control via I3C, one of I3C’s primary functions. Sensor and AP vendors can license the entire package of I3C, CSI and C/D-PHY from Arasan.
MIPI I3C is a chip-to-chip interface that can connect all sensors in a device to the application processor. It consolidates the features of i2c, SPI and UART into a simple two wire interface. The specification achieves clock rates up to 12.5 MHz and provides options for higher performance, high-data rate modes. Another key advantage is that it can be implemented using standard I/O’s on a CMOS process. I3C is also a low power interface using a fraction of the power consumed by i2c for the same performance.
Arasan I3C has already been licensed by early adopters and semiconductors incorporating our IP will hit the market this year.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, HDK, software stacks and optional customization services. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
About the MIPI Alliance
MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. Founded in 2003, the organization has more than 275 member companies worldwide, more than 15 active working groups, and has delivered more than 45 specifications within the mobile ecosystem in the last decade. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit http://www.mipi.org.
|
Arasan Chip Systems Hot IP
Related News
- New MIPI I3C Host Controller Interface Speeds Sensor Integration
- Arasan Announces MIPI I3C IP Cores compliant to the MIPI I3C Specifications v1.1
- Arasan announces its next generation of C-PHY/ D-PHY Combo IP Core compliant with the latest MIPI Specifications
- Arasan Announces MIPI D-PHY IP compliant to the latest MIPI D-PHY v2.1 Specifications for TSMC 16nm
- Arasan Announces MIPI D-PHY IP compliant to the latest MIPI D-PHY v2.1 Specifications
Breaking News
- Tenstorrent Expands Deployment of Arteris' Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions
- Siemens' Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle
- EnSilica plc - Audited Full Year Results for the Year Ended 31 May 2024
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
Most Popular
- Arm's power play will backfire
- Siemens strengthens leadership in industrial software and AI with acquisition of Altair Engineering
- Sondrel announces CEO transition to lead next phase of growth
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
E-mail This Article | Printer-Friendly Page |