SiFive Inc. and Andes Technology Corporation Join Forces to Promote RISC-V

Two Leading RISC-V Suppliers Agree to Cooperate to Further Promote RISC-V Adoption while Continuing to Aggressively Expand the RISC-V Ecosystem

Shanghai and San Mateo, Calif.—May 17, 2018— Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.

“RISC-V is providing a newfound freedom in silicon design, fostering stronger collaboration across the semiconductor industry. We’re excited to see SiFive and Andes partnering to expand the RISC-V ecosystem, making it easier for other industry players to quickly bring to market innovative designs based on the free and open RISC-V ISA,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.

As a founding member of the RISC-V Foundation, Andes Technology is dedicated to bringing its expertise in low-power and high performance 32/64 bit processor cores to the development of the RISC-V ISA. For example, at the recent RISC-V Workshop in Barcelona, Andes proposed an extension to the RISC-V ISA based on the DSP ISA used in Andes’ successful D10 and D15 processors. In addition, Andes debuted four new RISC-V processor IPs with compliant floating-point and Linux support: the 64-bit NX25F and AX25, and 32-bit N25F and A25. Andes’ innovative ACE (Andes Custom Extension™) solution allows Andes' customers to construct unique system architecture and hardware/software partitioning by defining domain-specific acceleration instructions to provide the best optimization for their SoC designs. Offering technologies in processor, system architecture, operating system, software toolchains development, and SoC design platforms IP, Andes enables its customers to shorten time-to-market while developing high-quality silicon in the shortest design time.

SiFive’s cloud-based SaaS approach allows its customers to produce ASIC and IP solutions that meets their needs quickly and affordably. SiFive’s mission is to democratize access to custom silicon through its IPs and platforms. Since becoming available, the HiFive1 and HiFive Unleashed software development boards have been deployed in more than 50 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products shipped the industry’s first RISC-V SoC in 2016 and the industry’s first RISC-V Core IP with support for Linux in October 2017.

Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive has recently raised $50.6M in Series C funding to fund innovation and provide leadership in bringing highly disruptive RISC-V technologies to the marketplace.

RISC-V Enables Innovation

RISC-V is an open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, the RISC-V ISA delivers a new level of extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. As the focus of a new upsurge in technology, RISC-V has flourished around the world. RISC-V is the new open ISA. It can be reduced, modularized, customized, easily expanded, and enable the rapid development of a design ecosystem. A large and growing number of leading technology companies have joined the RISC-V Foundation. SiFive and Andes have chosen Shanghai as the ideal location to relay efforts in promoting RISC-V to the world.

RISC-V is an open, extensible ISA, and its applications include the emerging areas such as AI, IoT, and ADAS. Its expansive ecosystem is even more valuable. The RISC-V ISA is expected to have a bright future of computing design in China.

About SiFive

SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Western Digital, Intel, SK Telecom, and Huami. For more information, visit www.sifive.com.

About Andes

Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications.
The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion.
To meet the demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include N25/NX25 and upcoming N25F/NX25F and A25/AX25.
For more information about Andes Technology, please visit http://www.andestech.com/.

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