English
Andes Certifies Imperas Models and Simulator as a Reference for Andes RISC-V Cores
Imperas Virtual Platform, Software Simulator and Models for AndesCore N25 and NX25 Processors Now Certified as a Reference by Andes Technology Corp.
OXFORD, England-- June 21, 2018--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, and Andes Technology Corporation, the prominent CPU IP provider, today announced that Andes has certified the Open Virtual Platforms™ (OVP™) instruction-accurate models and virtual platforms of the AndesCore™ N25 and NX25 IP processors. This rigorous certification program by Andes involves simulation and testing to their highest standard of accuracy, using a variety of real-world test cases and proprietary methods. N25 and NX25 are the AndeStar™ V5 32-bit and 64-bit architectures, based on the RISC-V technologies.
The certification of Imperas models and platforms helps the Andes ecosystem, developers and users because Imperas models and simulator can be used as a reference of these Andes cores, for developing operating systems and embedded software. Unlike hardware prototyping boards, these virtual platforms are flexible, extensible, easily available, and cost-effective solutions available across development teams.
Imperas is the leading commercial provider of RISC-V processor models and virtual prototype solutions, including both Andes N25 32-bit and NX25 64-bit cores, now certified by Andes. All Andes models are available from Imperas and the Open Virtual Platforms (OVP) website.
Andes is the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores for a full range of embedded electronics products, including low-cost embedded applications, data centers and artificial intelligence (AI), connected, smart and green applications, machine-learning accelerators, communications, security, IoT, and consumer applications.
Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior VP, commented, “Imperas virtual platform solutions and open-source models help accelerate embedded software development, debug and test for our customers. This certification demonstrates our great confidence in the accuracy and value of Imperas support for V5 AndesCore N25 and NX25 processors reference models and simulators for use by our customers, partners, and ecosystem.”
“We are proud to extend our long-standing relationship with Andes, and now announce Andes certification of our OVP models for their 32-bit/64-bit CPU cores, as a reference simulator,” said Simon Davidmann, president and CEO of Imperas.
Imperas delivers a comprehensive environment for embedded software development, debug and verification for Andes N25 and NX25 processors, including open-source Fast Processor Models; extendable virtual platforms including cores and peripherals; high-performance simulation; and OS-aware analytical tools for hardware-dependent multicore software development, debug and test. Imperas’ Extendable Platform Kits (EPKs) for Andes cores run FreeRTOS, and also support heterogeneous designs with mixtures of Andes processors and other vendors’ cores, including application processors.
Imperas will demonstrate these models and virtual platforms for RISC-V designs, based on Andes cores, at the upcoming Design Automation Conference (DAC) in June 2018.
These models of the Andes cores expand Imperas and OVP processor support to over 200 models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org.
About Andes Technology Corporation
Andes Technology, the first CPU IP supplier in Asia, has been developing innovative high-performance/low-power 32/64-bit processors and associated SoC platforms since its foundation in 2005. Its powerful CPU lineup covering entry-level, mid-range, high-end, extensible and security families has achieved design wins in numerous embedded applications across the world, making a cumulative record of over 2.5 billion SoC shipments containing Andes IP up to 2017. While delivering advanced features based on proprietary ISAs, Andes is also the first mainstream CPU vendor adopting the open standard RISC-V ISA. For more information please visit: http://www.andestech.com/.
About Imperas
For more information about Imperas, please see www.imperas.com.
|
||||||
Related News
- Andes certifies Imperas models and simulator as reference for new Andes RISC-V Vectors Core with lead customers and partners
- Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension
- NSITEXE Qualifies Imperas RISC-V Reference Models for Akaria Processors NS72A, NS72VA, and NS31A
- OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores
- Imperas announce first reference model with UVM encapsulation for RISC-V verification
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |