Moortec Supporting Today's Connectivity Boom with IoT Specific Embedded In-Chip Monitoring Subsystem Solution
Design Automation Conference (DAC), San Francisco -- June 25, 2018 -- Moortec, the in-chip sensing solutions provider, are pleased to announce today at the 2018 Design Automation Conference 2018 (DAC) the availability of a smaller scale, lower power, Internet-of-Things (IoT) focused embedded monitoring subsystem, targeting TSMC’s 40ULP (Ultra Low Power) process technology.
To support the rapidly evolving IoT landscape, today’s System-on-Chip (SoC) designs require solutions adapted to specific market constraints, which includes power efficiency and device reliability. Moortec’s new monitoring subsystem is developed specifically to physically monitor dynamic and static conditions deep within IoT enabled edge devices, hence enabling tight control over thermal, voltage supply and operational speed conditions. The product is therefore aimed at enabling chip developers to optimise power performance for their low-power end-use applications.
So far, chip monitoring solutions from Moortec have targeted applications areas such as Datacentre & Enterprise, Automotive, AI, Mobile, Consumer and Telecommunications, which utilise advanced node CMOS technologies. With this announcement the company has now made available a highly targeted Process, Voltage and Temperature (PVT) monitoring subsystem variant helping to alleviate the challenges faced by the IoT design community.
Moortec’s IP solution, being the first in its range of IoT targeted products, has been developed for TSMC’s 40nm ULP CMOS technology. By detecting process variability for each chip manufactured and monitoring the dynamic changes to temperature and voltage supply conditions, the IP can be used to enable continuous Dynamic Frequency and Voltage Scaling (DVFS) and Adaptive Voltage Scaling (AVS) optimisation schemes. The subsystem delivery also includes a sophisticated PVT Controller with AMBA APB interfacing, supporting multiple monitor instances, statistics gathering, production test access support as well as other compelling features.
“We understand that the developers of IoT edge devices need deterministic, reliable and highly power efficient solutions,” said Stephen Crosher, CEO of Moortec. “Our new IoT specific range of monitoring IP solutions will allow in-chip conditions to be accurately sensed and tightly controlled, allowing our customers to develop compelling IoT connected products.”
About Moortec
Established in 2005, Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimisation, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production. Moortec’s high-performance analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the consumer, mobile, automotive, high performance computing and telecommunications sectors. For more information, please visit www.moortec.com
|
Related News
- Moortec's In-Chip Sensing Fabric Enables Deeply Embedded Monitoring of Dynamic Conditions for Picocom's Baseband SoC for 5G Small Cells
- Moortec's In-Chip Monitoring Subsystem Supports Uhnder in Groundbreaking Digital Automotive Radar-on-Chip
- Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem
- Moortec's 7nm In-Chip Monitoring Subsystem IP chosen by Esperanto Technologies to optimise performance and reliability in its high-performance AI Chip
- Moortec announce their Embedded In-Chip Monitoring Subsystem on TSMC 12FFC
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |