Terminus Circuits Brings Complete ASIC Solutions to DesignShare
SiFive adds Terminus Circuits to include interconnect solutions, speeding time-to-market for leading RISC-V platform ecosystem
SAN MATEO, Calif. – July 10, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Terminus Circuits, a provider of interconnect solutions, has joined the expanding DesignShare economy. Through DesignShare, Terminus Circuits will offer complete ASIC solutions for products that are modular and scalable.
“At Terminus Circuits, we strive to offer our partners the best off-the-shelf, high-speed serial link products with high throughput and low latency,” said Dr. Sankar Reddy, founder and CEO of Terminus Circuits. “Through DesignShare, we hope to empower more system designers to create the future generations of enterprise-class servers, networks and storage products based on the SiFive Freedom platform.”
The DesignShare model democratizes access to custom silicon, allowing any company, maker or inventor to create an entirely new range of applications. The DesignShare program helps remove traditional barriers to entry that have blocked users from developing custom silicon by providing companies with low- or no-cost IP, reducing the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization.
“Terminus Circuits contributions to the DesignShare ecosystem provides engineers faster and easier access to interconnect solutions,” said Shafy Eltoukhy, VP of operations and head of the DesignShare program. “The RISC-V architecture continues to grow significantly, and with Terminus Circuits as part of the DesignShare movement, it will create simpler processes for system developers to employ RISC-V in their future designs across a wide range of implementations.”
Since the launch of the DesignShare ecosystem, the initiative has granted engineers access to a wide range of technology. In addition to ASIC solutions, developers can include cryptographic cores, embedded analytics, debug and trace technology, embedded, reconfigurable FPGA and logic-based, non-volatile memory to their SoCs. For more information about DesignShare visit https://www.sifive.com/designshare/.
About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit www.sifive.com.
About Terminus Circuits
Terminus Circuits offers high-speed, serial-link IPs and provides interconnect solutions across many standards like USB.org, PCIe-SIG, IEEE, SATA etc. Our products are an integral part of any HPC systems, providing the interconnect solutions that scale bandwidth and deliver end-to-end signal integrity in next-generation platforms. These robust interface IPs are available for different foundries and broad spectrum of process technologies. Terminus Circuits delivers low power, small form factor, low latency, integrated clocking, interconnect IPs that are pervasive in virtually all of today’s enterprise solutions in big data, digital storage and networks. For more information, visit www.terminuscircuits.com.
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Terminus Circuits Hot IP
Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
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