Credo Demonstrates Industry Leading SerDes on TSMC's 7nm Process at TSMC 2018 OIP Forum and Technology Symposium in Amsterdam
Enabling next generation 100G, 200G, and 400G Networks
Amsterdam, The Netherlands, July 20, 2018 – Credo, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it will demonstrate its advanced high performance, low power SerDes IP offerings at next week’s TSMC 2018 OIP Forum and Technology Symposium in Amsterdam. Credo will be featuring single-lane rate 56G PAM4 SerDes operating in both TSMC 12nm and 7nm process technology nodes.
“Working closely with TSMC as an OIP IP Alliance partner is enabling the rapid availability of our core SerDes technology on TSMC’s advanced process nodes,” said Jim Bartenslager, director of business development of Credo. “Our mutual customers with TSMC are excited about moving faster to 7nm and 12nm with proven high performance interconnects and our close relationship with Open-Silicon provides a path to complete system-level ASIC integration.”
The wide range of Credo SerDes IP solutions implemented in TSMC’s most advanced process technology nodes enables ASIC, ASSP, and SoC designers to meet the power and performance requirements of a variety of applications including switching, general purpose computing, artificial intelligence, and machine learning all of which are fueling expansion in next generation data center, enterprise, and telco networks.
- WHERE: TSMC Open Innovation Platform Ecosystem Forum, Hilton Amsterdam Airport Hotel, Schiphol Boulevard 701, Amsterdam, 1 118BN Netherlands
- DEMOS: Open-Silicon (Custom SoC Partner Booth)
- WHEN: July 23-24, 2018
- WHAT: The TSMC OIP Forum and Technology Symposium brings together
- WHERE: TSMC's design ecosystem companies and TSMC customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event
About Credo
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. The company makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced process nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo has offices in Milpitas, Taiwan, Shanghai and Hong Kong.
For more information: www.credosemi.com
|
Credo Semiconductor Hot IP
Related News
- Credo First to Publicly Demonstrate 112G SerDes in 7nm at TSMC's 2018 China OIP Forum
- Credo Demonstrates 112G PAM4 and 56G PAM4 SerDes IP Solutions at TSMC 2018 Technology Symposium
- Credo Demonstrates Single-Lane 112G and 56G PAM4 SerDes IP Solutions at TSMC 2017 OIP Ecosystem Forum
- Credo Demonstrates Single-Lane 112G and 56G PAM-4 SerDes IP at TSMC OIP Forum
- M31 demonstrates high-speed interface IP development achievements on TSMC's 7nm & 5nm process technologies
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |