IBM and Synopsys Accelerate Post-FinFET Process Development with DTCO Innovations
Synopsys Manufacturing, IP, and Design Implementation Technologies Enable Industry's Only Complete DTCO Flow
MOUNTAIN VIEW, Calif. -- Aug. 15, 2018 -- Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with IBM to apply design technology co-optimization (DTCO) to the pathfinding of new semiconductor process technologies for post-FinFET technologies. DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations using design metrics, starting with an early pathfinding phase before wafers become available. The collaboration will extend the current Synopsys DTCO tool flow to new transistor architectures and other technology options while enabling IBM to develop early process design kits (PDKs) for its partners to assess the power, performance, area, and cost (PPAC) benefits at IBM's advanced nodes.
"Process technology development beyond 7 nanometers requires the exploration of new materials and transistor architectures to achieve optimum manufacturability, power, performance, area, and cost. A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options," said Dr. Mukesh Khare, vice president of Semiconductor Research, IBM Research Lab. "Our DTCO collaboration with Synopsys allows us to efficiently select the best transistor architecture and process options based on metrics derived from typical building blocks, such as CPU cores, thus contributing to faster process development at reduced cost."
In this collaboration, IBM and Synopsys are developing and validating new patterning techniques with Proteus™ mask synthesis, modeling new materials with QuantumATK, optimizing new transistor architectures with Sentaurus™ TCAD and Process Explorer, and extracting compact models with Mystic. Design rules and process assumptions derived from these process innovations are used to design and characterize a standard cell library while Fusion Technology™ at the block level using the Synopsys physical implementation flow based on IC Compiler™ II place-and-route, StarRC™ extraction, SiliconSmart® characterization, PrimeTime® signoff, and IC Validator physical verification benefits the evaluation of PPAC.
The scope of the joint development agreement covers multiple facets, including:
- DTCO to optimize transistor- and cell-level design across routability, power, timing, and area
- Evaluate and optimize new transistor architectures, including gate-all-around nanowire and nanoslab devices, with process and device simulation
- Optimize variation-aware models for SPICE simulation, parasitic extraction (PEX), library characterization, and static timing analysis (STA) to accurately encapsulate the effects of variation on timing and power for highest-reliability design with least over-design and design flow runtime overhead
- Gather gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits
"Synopsys has developed the only complete DTCO solution, from materials exploration to block-level physical implementation," said Dr. Antun Domic, chief technology officer at Synopsys. "IBM's extensive process development and design know-how makes them an ideal partner for extending our DTCO solution to post-FinFET technologies."
For more information on DTCO, visit www.synopsys.com/DTCO.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys and UMC Collaborate to Accelerate Development of UMC's 14-nm FinFET Process
- Synopsys and Intel Foundry Accelerate Advanced Chip Designs with Synopsys IP and Certified EDA Flows for Intel 18A Process
- Continental and Synopsys Provide Vehicle Digital Twin Capabilities to Accelerate Software Development
- Socionext Begins Development of SoCs for Advanced ADAS and AD Using 3nm Automotive Process
- Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Advanced 4nm RF FinFET Process
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |