5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+
sureCore Opens Low-Power SRAM IP Customization Service
Process independent and silicon proven
Sheffield, England - September 25, 2018 - sureCore Ltd. announces a low-power, SRAM IP, application-centric, customization service that delivers specific power and performance requirements for wearable, wireless, augmented reality and IoT devices whose requirements go beyond standard low-power memory IP.
sureCore's application-centric, patented and silicon-proven, low-power design techniques prioritize power optimization over speed and area. The new service covers a wide spectrum of memory requirements covering multiple read/write ports, ultra-low leakage retention modes, low dynamic power, near-threshold operation, write masking and BIST/DFT support.
The sureCore service develops memory variants including SRAM and Register Files based on either standard foundry or custom bit cells, the latter capable of delivering ultra-low operating voltages, improved leakage characteristics and improved performance.
The application-centric service is rooted in sureCore's innovative design approach and innovative memory architectures that include:
- Segmented arrays and bit line voltage control that delivers optimal dynamic power and performance.
- SMART-Assist circuitry for near-threshold operation across process and temperature extremes.
- Highly granular sleep modes, coupled with independent sub-banks.
- Custom single and multi-port bit cells.
- Pipelined read circuitry that meets demanding performance goals.
"Today's emerging markets aren't playing by yesterday's rules and SoC architects developing cutting edge low-power devices can no longer make do with standard memory IP," explains Eric Gunn, sureCore's Chief Operating Officer.
"A number of companies have come to us with very ultra-low, application-specific power and performance targets that demand "out-of-the-box" thinking to achieve record-setting energy efficiency," says sureCore's CEO, Paul Wells.
The new customization service produces results based on a rigorous verification regime, which incorporates statistical, parametric and physical validation, and ensures that sureCore's application-centric memories meet demanding quality requirements. Design flows based on industry-leading, memory characterization tooling delivers multiple PVT corners quickly, accurately and automatically. All industry-standard EDA views are supported.
sureCore customized ultra-low power memory IP is built to exact specifications that hit dynamic power targets, operates at near-threshold voltages, delivers multiple read/write ports and provides a suite of comprehensive sleep modes that meets challenging leakage targets.
For additional information, please go to www.sure-core.com
About sureCore
sureCore Limited is an SRAM IP company based in Sheffield, UK, developing low power memories for current and next generation, silicon process technologies. Its award-winning, world-leading, low power SRAM design is process independent and variability tolerant, making it suitable for a wide range of technology nodes. This IP helps SoC developers meet challenging power budgets and manufacturability constraints posed by leading edge process nodes.
|
Related News
- sureCore Delivers Customised Low Power SRAM for Data Intensive Designs
- Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family
- SiliconBlue Introduces New iCEman65 Evaluation Kit for Ultra Low-Power, Single-Chip iCE65 SRAM FPGAs
- MOSAID Introduces SRAM IP with Industry's Lowest Leakage - Broad IP Platform Enables Fast, Low-Power, Low-Leakage Designs
- Taiwan's Etron, TSMC claim smallest low-power 8-Mbit SRAM with 0.15-micron process
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |