Synopsys Advances Test Fusion Technology with Test Points to Reduce Manufacturing Costs and Boost Quality
Accelerates Achieving Test Goals While Meeting Power, Performance, and Area Targets
MOUNTAIN VIEW, Calif., Oct. 29, 2018 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of Test Fusion technology with new test point functionality, providing design teams with powerful design-for-test (DFT) circuit modifications to reduce silicon test costs by an average of forty percent and increase defect detection while meeting design targets for power, performance, and area. Test Fusion ensures the test points avoid introducing routing congestion and minimize area impact, in contrast to traditional test point implementation techniques. RTL designers can easily deploy test points with a single step that automatically combines Synopsys' SpyGlass® DFT ADV testability analysis, DFTMAX™ design-for-test, and Synopsys synthesis products, then run TetraMAX® II automatic test pattern generation (ATPG) to create efficient silicon manufacturing tests. The solution is fully certified to comply with the ISO 26262 automotive functional safety standard and is widely deployed among semiconductor manufacturers.
To meet lower cost and increasing quality requirements, semiconductor manufacturers seek new technologies to improve detecting defective silicon prior to shipment. Several industry segments, such as automotive, are challenged to meet manufacturing test cost goals while achieving quality levels for their integrated circuits (ICs) of less than one defective part per million. Synopsys test points assist meeting these requirements by modifying the design to improve the ability of TetraMAX II to generate silicon test programs. SpyGlass DFT ADV analyzes designs and determines the most optimal and effective locations for test points that both decrease test pattern volume and increase defect coverage. Test Fusion technology ensures DFTMAX and Synopsys synthesis tools work in combination to implement the test points at the selected locations while minimizing routing using physical design data. Furthermore, Test Fusion provides an unprecedented reduction of area and congestion by enabling multiple test points to share a single test register based on physical proximity.
"Semiconductor companies are increasingly concerned about meeting manufacturing test quality and cost goals while achieving IC area, power, and performance goals within predictable design schedules," said Steve Pateras, senior director of marketing for Test Automation in Synopsys' Design Group. "Physically-aware test points are just one of several innovative Test Fusion technologies we are bringing to market to address this growing challenge."
For more information on the comprehensive Synopsys Test solution, visit www.synopsys.com/test.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys Advances Silicon Lifecycle Management to Accelerate Data Transport and Significantly Reduce Test Time
- Synopsys Announces DFTMAX Ultra to Significantly Reduce Silicon Test Costs
- Synopsys Advances Test and Yield Analysis Solution for 7-nm Process Node
- Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs
- TranSwitch Selects eSilicon to Reduce Manufacturing Costs and Streamline Design-to-Manufacturing Process
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |