0-In Welcomes Seasoned Industry Veterans Rick Hyman and TJ Boer to Executive Team
Rick Hyman named VP Worldwide Sales; TJ Boer named VP North American Sales
SAN JOSE, Calif. - December 18, 2002- Today 0-In Design Automation, the Assertion-Based Verification Company, welcomed two vice presidents to its executive team: Rick Hyman joined the company as vice president of worldwide sales, and TJ Boer joined as vice president of North American sales. Both Mr. Hyman and Mr. Boer have successfully grown global sales teams and field application organizations, and have been instrumental in creating and managing strategic partnerships with key semiconductor customers.
"0-In has built its technology leadership position in assertion-based verification over the past few years," said Emil Girczyc, 0-In president and CEO. "With Rick and TJ on board, we are launching the next phase of our company, which is to strengthen our market leadership position. Rick and TJ have the experience and track record to build strong teams, develop strategic accounts, and position products for widespread global adoption. We're delighted to welcome them to the 0-In team."
Mr. Hyman has more than 20 years of experience in engineering and sales management, and was most recently president and CEO of TeraOptics Networks, an optical switching and routing company that last year was named Fabless Startup of the Year by the Fabless Semiconductor Association. Before that he held sales management positions at Silicon Spice, MMC Networks, and NVIDIA; and was at Synopsys for five years in sales and marketing management. He holds a BS in chemical engineering from the University of Washington. Mr. Hyman and his wife, Cheryl, host a charity dinner every year benefiting the Lance Armstrong Foundation.
Mr. Boer has more than 15 years of experience in engineering, sales and marketing management, most recently as senior vice president of sales at Sequence Design, where he managed U.S. and Japan sales and operations. Before that, he was at Synopsys for over eight years, most recently as director of synthesis marketing. Mr. Boer holds a BSEE degree from Loyola Marymount University in Los Angeles and an Executive MBA from Stanford University.
"In the last few years I've seen firsthand the growing problem of IC verification," said Mr. Hyman. "Design schedules are dominated by verification, and the business issues that result from these design schedules are seen every day in missed market windows and cancelled projects. Today it takes about $20M to complete a design, and $2M to make the mask. Companies can't afford to respin and they can't slip the schedule."
"These business pressures create a tremendous opportunity for 0-In. Assertions are to verification what synthesis was to design, and 0-In is the obvious leader in assertion based verification. With people like 0-In chairman Curt Widdoes, founder Steve White, and Emil, we will continue to lead the industry and make assertion-based verification mainstream, just as synthesis is today."
"The combination of break-through verification technology and an outstanding team made me jump at this opportunity to grow the customer base," said Mr. Boer. "I'm very impressed with the maturity level of the 0-In products and the value they provide to customers."
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
0-In® is a registered trademark of 0-In Design Automation, Inc.
|
Related News
- 0-In Welcomes Mentor Graphics to its Check-In Partner Program
- Momentum Builds for Assertion-Based Verification: 0-In Welcomes Averant and Bridges2Silicon as Check-In Partners
- Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology
- Renesas Technology Integrates Mentor Graphics 0-In Assertion Synthesis for Assertion Based Verification Flow
- Mentor Graphics Enters Into Agreement to Acquire 0-In Design Automation
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |