Updated HBM Standard Geared for HPC, Networking
By Gary Hilson
EETimes, January 18, 2019
TORONTO — High Bandwidth Memory (HBM), like many other memory technologies, is being adopted for emerging use cases that didn’t exist at its inception because of specific characteristics such performance, capacity and power consumption. But it won’t be long before there’s pressure to improve upon them as adoption in newer scenarios takes off.
The Jedec Solid State Technology Association’s most recent update to the JESD235 HBM DRAM standard focuses on meeting the needs of applications in which peak bandwidth, bandwidth per watt, and capacity per area are critical metrics. Such applications include high-performance graphics, network and client applications, and high-performance computing.
E-mail This Article | Printer-Friendly Page |
Related News
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies
- GUC Announces 2.5D and 3D Multi-Die APT Platform for AI, HPC, Networking ASICs
- JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard
- GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS Technology Validating 7.2 Gbps HBM3 Controller and PHY, GLink-2.5D and 112G-LR SerDes IPs
Breaking News
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition