AccelerComm introduces software only 5G NR channel coding IP at MWC Barcelona 2019

AccelerComm to demonstrate commercially ready software-only IP for 5G NR in support of virtualized networks.

12th February 2019, Southampton, UK -- AccelerComm has today announced the release of a software-only implementation of 3GPP-compliant polar coding IP for 5G NR (New Radio). The polar chain is optimised for the Intel FlexRAN reference architecture.

The introduction of AccelerComm’s IP enables developers and manufacturers to create soft implementations of infrastructure solutions that meet the performance required by the 3GPP specification while providing maximum flexibility. As the market embraces open architectures defined by the O-RAN alliance, the availability of complete 3GPP-compliant channel coding chains optimised for implementation in software-only, FPGA or ASIC platforms will enable AccelerComm’s customers to accelerate 5G technology developments while maximising spectrum efficiency through excellent BLER performance.

AccelerComm’s CTO, Professor Rob Maunder, commented: “Flexibility is key to success when developing advanced communications and these high performance standardized architectures in the wireless infrastructure market are enabling that flexibility while helping to reduce development time. ”

The AccelerComm polar solution is available today and can be seen on the Great Britain and Northern Ireland stand in Hall 7 at MWC Barcelona (February 25^th– 28^th, Stand 7A11.19).

Polar coding has been selected by 3GPP as part of the 5G NR specification. AccelerComm’s high performance offering is 100 percent compliant with the standard and covers the total processing chain, from the 3GPP TS 38.212 standard including the encode / decode engine, channel interleaving, rate matching, and CRC.

AccelerComm’s software Physical Uplink Control Channel (PUCCH) decoding IP is fully compatible with 3GPP New Radio v15.4.0, The Block Error Rate (BLER) performance of its PUCCH decoding IP and the average processing time of its SCL decoder core are fully characterised in the datasheet, which is available from the link below. AccelerComm’s decoding IP offers superior processing throughput; up to 2.5 times higher than the Intel SCL decoder core provided in the FlexRAN SDK, and offers up to 0.3dB improved BLER performance. This enables more users to be served with less compute power, achieving greater capacity on a given cell.

Accelercomm product demos at MWC Barcelona are:

1. Polar software 3GPP compliant core implementation:
   • Polar decoder running on an Intel X-Series processor with AVX 512 support.
2. Polar FPGA 3GPP compliant chain implementation:
   • Polar encode and decode chain running on Intel's Arria 10 and Xilinx Ultrascale FPGA.
   • Polar uplink encode and decode chain running on Intel Cyclone 5 FPGA.
3. LDPC FPGA 3GPP compliant core implementation:
   • LDPC decoder core running on Intel's Arria 10 and Xilinx Ultrascale FPGAs
4. Turbo FPGA 3GPP compliant core implementation:
   • Turbo decode and encode running on Intel's Stratix V showing 10x reduced latency ideal for 4G URLLC.

About AccelerComm

AccelerComm provides LDPC, polar and turbo solutions which enable optimal performance of communication systems, and solves the challenges that would otherwise limit the speed of next generation communications, namely the error correction decoding that is required to overcome the effects of noise, interference and poor signal strength.

For further information visit: www.accelercomm.com.

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