OCP 2019: eSilicon to demonstrate 56G DSP SerDes over a 5-meter cable assembly in Samtec booth
March 12, 2019 -- San Jose, Calif. -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will demonstrate its 7nm FinFET-class SerDes IP product at OCP 2019.
What
SerDes Demonstration: Samtec booth at OCP
San Jose Convention Center
Thursday-Friday
March 14-15, 2019
Using Samtec ExaMAX Backplane Connector paddle cards and a five-meter ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes.
The demonstration will drive four high-speed SerDes lanes in three configurations:
- CPRI NRZ modulation with point-to-point links
- 50G Ethernet PAM4 modulation with point-to-point links
- 56 Gbps PAM4 modulation with point-to-point links
Real-time data associated with all channels will also be displayed to demonstrate the robustness and low power of the device, including:
- Voltage histograms, pre- and post-DSP
- Signal-to-noise ratio (SNR)
- Equalization
- Eye diagrams
- Bit error rate (BER) monitor
About OCP
March 14-15, 2019
San Jose Convention Center
San Jose, Calif., USA
The 2019 Open Compute Project (OCP) Global Summit brings together more than 3,400 key decision makers, executives, engineers, developers and suppliers. Together, they help grow, drive and support the open hardware ecosystem in, near and around the datacenter and beyond.
About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
|
Related News
- OFC 2019: eSilicon to demonstrate two 7nm IP products, 56G DSP SerDes over a 5-meter Samtec cable assembly and a complete HBM2 PHY subsystem
- DesignCon 2019: eSilicon to demonstrate 7nm 56G DSP SerDes over 5-meter Samtec cable assembly
- Linley Spring Processor Conference 2019: eSilicon to demonstrate 7nm DSP SerDes over a 5-meter cable assembly and present on IP platforms
- ISSCC 2019: eSilicon to present a paper and demonstrate 7nm 56G DSP SerDes operation over a five-meter cable assembly
- ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies
Breaking News
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Celestial AI Announces Appointment of Semiconductor Industry Icon Lip-Bu Tan to Board of Directors
- intoPIX and EvertzAV Strengthen IPMX AV-over-IP Interoperability with Groundbreaking JPEG XS TDC Compression Capabilities at ISE 2025
- TeraSignal Demonstrates Interoperability with Synopsys 112G Ethernet PHY IP for High-Speed Linear Optics Connectivity
- Quadric Opens Subsidiary in Japan with Industry Veteran Jan Goodsell as President
Most Popular
- Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
- 创飞芯宣布其反熔丝一次性可编程(OTP)技术在90nm BCD 工艺上实现量产
- Alphawave Semi to Showcase Innovations and Lead Expert Panels on 224G, 128G PCIe 7.0, 32G UCIe, HBM 4, and Advanced Packaging Techniques at DesignCon 2025
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Mixel Announces the Opening of New Branch in Da Nang, Vietnam
E-mail This Article | Printer-Friendly Page |