Vidatronic Sponsors Design & Reuse's IP SoC Days Conference 2019 in Santa Clara
COLLEGE STATION, TX – April 1, 2019 – Vidatronic, Inc., a leading licensor of power management circuit and CMOS radio frequency (RF) power intellectual property (IP), today announced it is a sponsor of the Design and Reuse (D&R) annual IP SoC Days 2019 Conference (www.design-reuse.com). The conference will be held April 9, 2019 at the Hyatt Regency Santa Clara in Santa Clara, CA. Vidatronic will be in Booth 1 in the mezzanine area of the hotel.
On Tuesday, April 9 at 2:00 PM Vidatronic’s Vice President of Sales and Business Development, Stephen Nolan, will present, Power Management for Internet of Things (IoT) SoC Development, a session designed to help attendees gain a better understanding of how to use power management IP blocks in their IoT SoC designs to differentiate their products and get to market faster.
“This is our first year at the IP SoC Days Conference,” said Stephen Nolan. “We are excited to have this opportunity to show high-level engineers and executives how, by integrating Vidatronic IPs into their SoC designs, they can accelerate their time to market with reduced risk, while seeing significant performance improvements and cost-savings. This year has already been a very exciting year of growth for Vidatronic and we welcome this chance to share our latest IP products in small-process geometries with the IP community.”
“We are delighted to welcome our most valuable IP providers, like Vidatronic, to present their latest innovations at IP SoC Days 19 in Santa Clara. The attention from major semiconductor players this year appears to be excellent,” commented Gabrièle Saucier, CEO of D&R. “This will be an exciting event and definitively proves D&R’s favorite slogan: “IP providers are the innovation seed of the Electronic industry.”
The D&R IP SoC Days Conference is the annual meeting in Silicon Valley for IP providers and IP consumers to share information about technology trends, innovative IP/SoC products, breaking IP/SoC news, IP market evolution, and more. In addition to Vidatronic, D&R welcomes guests and sessions from ARM, Synopsys, Intel, and more.
Additional Information:
Register for the IP SoC Days Conference: https://www.design-reuse.com/ipsocsantaclara2019/registration/
|
Related News
- Sankalp Semiconductor to Exhibit & Present at Design & Reuse IPSoC Santa Clara 2019
- Arasan Chip Systems to deliver a keynote at Design & Reuse's IP-SoC Day seminar in Santa Clara
- SiliconAuto adopts Siemens' PAVE360 to accelerate pre-silicon ADAS SoC development
- NUMEM & IC'ALPS Collaborate to Develop an ultra-low-power SOC for Sensor and AI applications
- Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |