Sofics Releases Analog IO's and ESD protection clamps for Advanced Applications using TSMC 7nm FinFET process
Proven technology significantly reduces risk, time-to-market and overall cost
Belgium, April 8, 2019 – Sofics bvba, a leading semiconductor integrated circuit IP provider announced that it has expanded its TakeCharge® Electrostatic Discharge (ESD) and Analog IO portfolio with solutions for the TSMC 7nm FinFET process. Sofics has already verified its TakeCharge Analog IO’s and ESD protection clamps on a wide variety of processes, including CMOS, SOI and FinFET technologies across various fabs and foundries.
Sofics is a foundry independent semiconductor IP provider that has supported 60+ fabless companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. Most foundries provide I/O libraries for free. However, for several application types the general purpose I/Os introduce all kinds of limitations. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. The technology is silicon and product proven in more than 3000 mass produced IC-products.
Interface ESD protection in FinFET technology is challenging. The FinFET circuits fail easily under stress and the traditional ESD concepts are not effective anymore. Moreover, for advanced applications free GPIO libraries introduce limitations on the circuit performance due to excessive parasitic capacitance, leakage or voltage tolerance.
“Our specialized interface solutions enable product reliability and manufacturing yield for the leading-edge applications in the world’s most advanced foundry process”, said Koen Verhaege, CEO of Sofics. “This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable high speed, higher operating voltages and complex architectures.“
“Whether it is 0.18um CMOS or 7nm FinFet does not really matter. Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution”.
TakeCharge cells as well as robust I/O solutions are readily available from Sofics.
About Sofics
Sofics stands for “Solutions for ICs”. We are a foundry independent IP provider with a track record in on-chip robustness for ESD, EOS and EMC. Leveraging an extensive patent portfolio, more than 70 licensees, product proof in more than 50 processes, generates on average every day one new IC volume production release including Sofics IP.
|
Related News
- Sofics releases Analog I/O's and ESD clamps for TSMC N5 process
- Sofics Analog I/O's and ESD clamps proven for TSMC 16nm, 12nm and 7nm FinFET processes
- Sofics releases pre-silicon analog I/O's for high-speed SerDes for TSMC N5 process technology
- Sofics releases its ESD technology on TSMC 3nm process
- Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Advanced 4nm RF FinFET Process
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |