Rambus Announces Tapeout and Availability of 112G Long Reach SerDes PHY on Leading-edge 7nm Node for High-Performance Communications and Data Centers
SerDes PHY delivers leading-edge performance and power efficiency for next-generation SoCs in data-intensive applications
SUNNYVALE, Calif. – April 16, 2019 – Today Rambus Inc. (NASDAQ: RMBS) announced its newest portfolio solution of 112G Long Reach (LR) SerDes PHY on a leading-edge 7nm process node for next-generation terabit switches, routers, optical transport networks (OTNs), and high-performance networking equipment. As the industry rapidly transitions to 400GB and 800GB wired communication applications, 112G is a key building block necessary to support the ever-growing demand for more bandwidth in data center and network applications, doubling the data rate of 56G SerDes. Rambus is at the forefront of implementing 112G design to address the long-reach backplane requirements for next-generation data-intensive applications.
This high-speed PHY provides the optimal combination of power efficiency, performance and area, adding to Rambus’ leading-edge large portfolio of silicon-proven intellectual property (IP), design tools and reference flows. With the introduction of 112G, this technology achieves higher performance to rapidly enable industry infrastructure for the 400GB and 800GB applications.
“By leveraging leading 7nm process technology, Rambus is enabling the next generation of Communications and Data Center applications,” said Hemant Dhulla, VP and GM of IP Cores, Rambus. “We’re excited to continue to expand our IP portfolio and deliver our customers top-of-the-line performance and flexibility for today’s most challenging systems, including solutions like our 112G LR SerDes PHY.”
This latest portfolio addition highlights Rambus leadership in high-speed SerDes PHY IP, leveraging the company’s long tradition of signal and power integrity expertise — remaining at the forefront of innovation in interface technology.
Rambus 112G Long Reach SerDes PHY
Rambus Modeled PAM-4 Signaling Transmit Eye
Technical Details
The will deliver enterprise-class performance across the demanding backplane environments beyond 30dB. To achieve this data rate requires an innovative SerDes architecture approach to meet the ever-growing data needs for high-speed data-intensive applications.
Key features of the Rambus 112G LR SerDes PHY include:
- Scalable ADC-based (analog-to-digital converter) architecture with support for PAM-4 and NRZ signaling
- DSP-based architecture for improved signal to noise ratio (SNR) and extended reach
- Configurable to provide power, performance and area (PPA) optimization for medium reach (MR) and long reach (LR) applications.
Availability and Additional Information
The Rambus 112G LR SerDes PHY is currently available for licensing and early access design customers can engage today.
With a near-term roadmap featuring industry-leading 112G solutions for extreme short reach (XSR), the Rambus industry-standard interface offerings are high-quality, complete PHY solutions designed with a system-oriented approach to maximize flexibility in today’s most challenging system environments. For more information on our latest high-speed SerDes PHY portfolio offerings, please visit rambus.com/serdes.
|
Related News
- Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
- Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center
- Synopsys Targets 400G Hyperscale Data Centers with High-Performance Ethernet IP
- Rambus Unveils 56G SerDes PHYs on Leading-Edge FinFET Technology
- Rambus Unveils PCIe 7.0 IP Portfolio for High-Performance Data Center and AI SoCs
Breaking News
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |