Moortec to Showcase its PVT Monitoring IP at TSMC China Technology Symposium
June 17, 2019 -- Moortec will be showcasing its range of PVT Monitoring Subsystem Solutions supporting advanced node processes at the TSMC 2019 China Technology Symposium, taking place on Tuesday 18th of June at the Shanghai International Convention Centre (SICC). Visit us at the event to discuss how your next SoC project could benefit from our highly accurate, highly featured in-chip monitors which provide solutions for thermal management, detection of supply anomalies and the identification of process corners.
Visit booth #36 to learn more about Moortec’s range of silicon proven, ‘off the shelf’ monitoring IP solutions. Moortec monitoring IP is used by a wide range of customers worldwide for monitoring and controlling conditions on-chip to optimise performance, save power, increase reliability and cut costs.
Moortec provide market leading high accuracy, highly featured PVT Subsystem IP for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies on 40nm, 28nm, 16nm, 12nm and 7nm. The Moortec Subsystem provides ASIC designers solutions for thermal management, detection of supply anomalies and the identification of process corners.
Of particular relevance at the event will be the continued focus on applications such as AI, Data Centre, Automotive, SSD Controllers and IoT. As a company Moortec are committed to expanding its advanced node in-chip monitoring portfolio while maintaining our focus as the leading PVT provider.
To arrange a meeting at this event please email ramsay.allen@moortec.com or visit www.moortec.com
About Moortec
Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies on 40nm, 28nm, 16nm, 12nm and 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimization, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production. Moortec’s high-performance analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the Automotive, AI, IoT, Datacenter, DTV, HPC and Networking sectors.
For more information please visit www.moortec.com
|
Related News
- Moortec to Showcase its PVT Monitoring IP at TSMC 2019 Technology Symposium
- Moortec To Showcase Its PVT Monitoring IP At the TSMC China OIP Ecosystem Forum in Nanjing
- Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara
- Moortec To Showcase Its PVT Monitoring IP At TSMC 2019 Boston Technology Workshop
- Moortec to showcase its advances in PVT in-chip monitoring for 40nm, 28nm, 16nm, 12nm and 7nm at ICCAD in Zhuhai China
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |