Cadence Announces First-to-Market DisplayPort 2.0 Verification IP
Cadence VIP drives early adoption of next-generation DisplayPort standard for mobile and automotive applications
SAN JOSE, Calif., 26 Jun 2019 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry’s first Verification IP (VIP) in support of the new DisplayPort 2.0 standard. The Cadence® VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.
For more information on Cadence VIP for DisplayPort 2.0, please visit www.cadence.com/go/displayportvip.
The latest Cadence VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard—enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance. The Cadence VIP for DisplayPort 2.0 offers the industry’s most comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimize verification predictability. Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.
Maurizio Paganini, EVP and COO at MegaChips, a highly innovative fabless semiconductor company in Japan, and a leading developer of semiconductors with expertise in analog, digital and MEMS technology, said: “Our team has successfully utilized the Cadence VIP for DisplayPort for previous versions of the specification, which enabled us to deliver advanced audio and video IP solutions for personal computing, mobile and consumer AV devices. We are happy to see Cadence deliver VIP for the DisplayPort 2.0 specification. The DisplayPort 2.0 specification will be supported in our next generation of products for mobile computing, enterprise connectivity, gaming, AR/VR and AV streaming systems.”
“By releasing the first-to-market VIP for DisplayPort 2.0, we’re enabling early adopters to ensure their designs comply with the specification while achieving the fastest path to IP verification closure,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “We have been working closely with early adopters of the spec, which has enabled us to provide a solid and high-quality verification IP for advanced designs for automotive, mobile and machine learning applications.”
The Cadence Verification IP portfolio, including the latest VIP for DisplayPort 2.0, is part of the broader Cadence Verification Suite and is optimized for Xcelium™ Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments. The Cadence Verification IP supports the company’s Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
|
Search Verification IP
Cadence Hot IP
Related News
- Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing
- SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
- Cadence Announces Industry's First Verification IP for HDMI 2.0
- Cadence Selects Chipidea's USB 2.0 IP For Its SoC Functional Verification Kit
- Cadence Expands Support for 3Dblox 2.0 Standard with New System Prototyping Flows
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |