Avery Design Systems Announces SimRegress and SimCompare
TEWKSBURY, MA. -- June 28, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimRegress and SimCompare for improved simulation verification productivity.
SimRegress provides the ability to capture and replay the simulation testbench stimulus without having to run the full testbench thus supporting improved methods for 3rd party IP debug using tests directly from the customer SoC verification environment. Converters from the Avery database to Verdi FSDB and SimVision are supported to generate and inspect the waveforms.
SimCompare provides a smart diff feature between RTL and gate-level simulation. SimCompare correlates RTL and gate-level signal names and transaction synchronization between the two simulations being compared. The SimDiff application is integrated with Verdi and SimVision to directly scope these respective waveforms and source code debug tools and windows for more detailed inspection.
|
Avery Design Systems Hot Verification IP
Related News
- Avery Design Debuts CXL Validation Suite
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Avery Design Systems Announces SimXACT-SA™ for Improved Sequential X-Verification
- Siemens expands industry-leading integrated circuit verification portfolio with acquisition of Avery Design Systems
- Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |