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New IP catalog from Terminus Circuits
July 16, 2019 -- Terminus Circuits announces the availability of it's AMS ( Analog Mixed Signal) IP design kits for TSMC 28nm HPC and HPC+ process technologies. This IP portfolio includes PCIe Gen4 with backward compatibility, USB 3.2 Gen 2x2 and its variants, MIPI M-Phy G4 with backward compatibility, PLL's (RO & LC) upto 16GHz with Spread Spectrum Clocking Generation, Reference clock PLL subsystems for PCIe, USB, MIPI Mphy, Ethernet SerDes, PVT compensated Resistor Termination, Current & Voltage bias circuitry.
Customer tape outs/road map IP tape outs of all these IPs are done/in-progress, expecting the Silicon Results by 3Q/4Q 2019.
These High Speed Serial Link IPs enable the system developers for edge computing, NOC ( network On Chip), Storage, AI, DL, 5G, big data and cognitive computing. Terminus Circuits IP portfolio enables it's customers to reach their PPA (Power, Performance, Area) requirement for their system level integration and for their USP ( Unique Selling Proposition).
About Terminus Circuits:
Founded in 2010, www.terminuscircuits.com, is the leading provider of protocol based high speed interconnects (PCIe, USB, MIPI, Ethernet SerDes) to OEM's for big data, AI, ML, Servers chips, 5G applications.
#PCIe #USB3.2 #MIPI MPhy #Ethernet SerDes #Big Data #5G #HPC #AL # DL
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Terminus Circuits Hot IP
Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process -
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
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Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
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Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
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Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
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