SCALINX new ASIC design center in SOPHIA-ANTIPOLIS, France
July 29, 2019 – To support its fast growth, SCALINX opened this month, in addition to its ASIC design centers in Paris and Caen, the third one in Sophia-Antipolis, France, offering services for custom designed Integrated Circuits.
“We are very excited to be opening our third ASIC design center, which has a highly educated team with tremendous IC design expertise, here in Sophia-Antipolis France” said Hussein Fakhoury, CEO of SCALINX. “Initially, this dynamic design team will consist of 5 engineers expecting rapid growth as we continue supplying application specific ICs to our customers, applying innovative art of signal conversion.”
The new design center in Sophia-Antipolis gives SCALINX the ability to augment the design support for its customers.
SCALINX is among the fastest growing and highly trusted companies in the Semiconductor Industry, designing signal conversion ASICs formed on its proprietary SCCORETM technology for Test & Measurement, Defense, Aerospace and Communications markets.
About SCCORETM technology - Smart Conversion CORE technology uses proprietary wide-band Continuous-Time ΔƩ A/D Converter architecture facilitating solutions where bandwidth vs. resolution trade-offs are implemented in programmable digital circuity. This technology leads to significant performance improvement and BoM saving.
|
Related News
- SCALINX expansion continues with ASIC design center in Caen, France
- Broadcom Debuts Industry's First 5nm ASIC for Data Center and Cloud Infrastructure
- Codasip Announces a New Design Center in France
- Rianta Releases 800G MACsec ASIC/SoC IP Core for Next-Gen Data Center and 5G Backhaul Applications
- Dream Chip opened new ASIC Design Center in Eindhoven, Netherlands
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |