iRoC announces new error protection for memories

M-RoCKIT Platform Boosts Error Correction Generation for SoC Designs

SANTA CLARA, Calif. -- Jan. 16, 2003 -- iRoC Technologies, a leader in the field of Infrastructure IP, announced today the release of the beta version of M-RoCKIT™, a new technology platform for automated generation, interconnection and insertion of advanced error correcting code (ECC) for protection against bit flips in embedded memories. Today's SoC designers are facing the double challenge of:

- Increased sensitivity of memories to bit flips for new technologies together with an increased amount of Mbits of memories on SoCs
- Increased diversity of memories in SoCs (over 100 memory types).

iRoC developed with the M-RoCKIT platform a wide set of protection solutions ranging from bit parity to ECC techniques to advanced proprietary solutions. This technology also includes a fast and versatile engine that automates the memory protection process and searches for low-cost error correction architectures. For an SoC with more than 100 memories, 50% of which need to be protected, designers adopting M-RoCKIT will reduce the design time by 4 times. This full protection is achieved while saving from 15% silicon overhead for non-maskable memories and up to 8 times for maskable ones. These proprietary solutions drastically reduce the speed penalty as well.

iRoC Announces New Error Protection for Memories
"This is the first commercially available tool in the field of memory bit flips protection. We strongly believe that this new type of Infrastructure IP will free fabless or IDM companies from a new, critical nanometer design risk in meeting the reliability specifications of their customers," said Eric Dupont, president and CEO of iRoC Technologies.

iRoC Memory Protection Design Approach
Bit flip occurrence is now a production concern for 0.13 µm technologies and current FIT (Failure In Time) rates do not apply anymore to actual customer needs for security, reliability and availability. As an example, system houses demand a certain soft error rate (SER) for SoCs and memories within their procurement process that is impossible to reach without bit flip protection.

Though ECC is a standard technique used by designers to protect memory or other devices, applying it "as is" in a complex SoC could add a significant cost burden and strap down performance.

iRoC's Advisor with 25 ECC architectures, included within M-RoCKIT, identifies and decides the optimized protection architecture to meet memory specifications and acceptable ECC impact in terms of area, performance and power consumption. M-RoCKIT's versatile ECC generation engine operates at the RT level and uses a simple set of instructions to embed and interconnect the correction block and its associated memory.

"We are making the fully tested M-RoCKIT available now to give our customers and prospective alliance partners time to plan for incorporating this unique technology into their upcoming advanced designs as soon as possible," added Mr. Dupont.

Availability
The M-RoCKIT data sheet is available today on www.iroctech.com. The beta version will be available for selected customers and alliance partners within Q1/03 while final product pricing and delivery will be within the first half of 2003.

About iRoC Technologies
iRoC is a semiconductor intellectual property (IP) company that licenses design solutions to completely stop unreliability trends and increasing of FIT rates of nanometer processes. iRoC offers a turnkey and total solution from technology process characterization, a family of Infrastructure IP building blocks for Robustness, along with their tool suite, and radiation test services for dies or systems qualification. More information on the company's products and services can be obtained at www.iroctech.com.

iRoC Technologies and M-RoCKIT, are registered trademarks of iRoC Technologies Corporation. All other company or product names may be trademarks of the respective companies with which they are associated.