MIPI Alliance Opens Access to its Debug and Trace Specifications
Publicly available specifications include newly released MIPI SneakPeek Protocol v2.0, with optimizations for low-bandwidth interfaces with applications for IoT
PISCATAWAY, N.J., September 11, 2019 – The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced that its debug and trace specifications are now publicly available for download.
MIPI debug and trace specifications give device developers a standard, layered set of interfaces and protocols to address debug requirements specific to mobile devices, providing an alternative to using dedicated debug and test equipment.
"Opening up access to MIPI debug and trace specifications will foster a more standardized debug environment, improving development processes and quality in and beyond the mobile device industry," said Joel Huloux, chairman of MIPI Alliance. "In addition to allowing more developers to use the specifications, this step will strengthen the ecosystem, leading to broader interoperability and a richer development environment.”
The nine available specifications include the following:
- MIPI SneakPeek Protocol (MIPI SPP) v2.0, the latest version of the standard communications protocol for debug and test applications, which includes MIPI TinySPP, a style of SneakPeek for low-bandwidth and potentially high-latency interfaces
- MIPI System Software-Trace (MIPI SyS-T), a universal data format for transmitting software debug and trace information
- MIPI Narrow Interface for Debug and Test (MIPI NIDnT), a specification that allows the use of functional ports on a device for debug/testing of finished products
- MIPI System Trace Protocol (MIPI STP), a base protocol for application-specific trace functions
- MIPI Trace Wrapper Protocol (MIPI TWP), a protocol enabling multiple source trace streams to be combined into a single trace stream
- MIPI High-Speed Trace Interface (MIPI HTI) and MIPI Parallel Trace Interface (MIPI PTI), for exporting trace data
- MIPI Gigabit Debug for USB (MIPI GbD USB) and MIPI Gigabit Debug for IP Sockets (MIPI GbD IPS), techniques for using the SPP and TWP protocols over USB and IP sockets
In addition, MIPI Alliance’s software specifications are publicly available to help streamline the software integration of components in mobile devices, as well as in mobile-connected designs targeted for IoT, automotive and other applications. These specifications allow developers to take a common software approach when loading drivers for different types of components from different vendors.
In conjunction with the public release of the nine debug and trace specifications, MIPI announced the availability of MIPI SPP v2.0. The specification introduces MIPI TinySPP, which is optimized for use with low-bandwidth and potentially high-latency interfaces such as MIPI I3C, the high-performance, low-power interface for links between sensors and application processors.
"The IoT explosion is creating demand for millions of small, low-powered devices, such as sensors, in mobile and mobile-influenced systems," said Enrico Carrieri, chair of the MIPI Debug Working Group and Principal Engineer in Debug Architecture with Intel Corporation. "With MIPI SPP v2.0, TinySPP extends SneakPeek so it can be used for efficient debugging of these devices."
MIPI SPP simplifies mobile device development by replacing the use of dedicated debug interfaces, such as JTAG, between a debug and test system (DTS) and a target system (TS). It abstracts the interface and uses the familiar mechanism of address-mapped read-and-write transactions to access components of the TS via memory agents. SPP can be used by multiple debug and test applications.
TinySPP introduces features that reduce the data transfer and overhead requirements for debug and test communications. These include a shorter minimum packet length of 4 bytes instead of 16 bytes, a smaller transaction byte field of 7 bits instead of 16 bits, and a short addressing system that reduces 64-bit or 32-bit addresses to 6 bits where possible.
In addition, MIPI SPP v2.0 defines packetized JTAG messaging. This messaging reduces the overhead involved in using JTAG to change state. New opcodes provided in both FullSPP and TinySPP eliminate the need for "bit-banging,” or exchanging long series of ones and zeros, which achieves the efficiency needed for low-bandwidth interfaces. SPP v2.0 can also use a single command to set up a polling loop rather than going in and out of shift state, which makes it better suited to high-latency interfaces.
MIPI SPP v2.0 and the other debug specifications are available for public download now.
MIPI Alliance encourages interested companies to consider joining MIPI to reap the full membership benefits, which include access to relevant licenses, and opportunities to participate in development activities, interoperability workshops and other events.
About MIPI Alliance
MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone manufactured today. Founded in 2003, the organization has over 300 member companies worldwide and 14 active working groups delivering specifications within the mobile ecosystem. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP tool providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit www.mipi.org.
|
Related News
- MIPI Alliance Releases A-PHY v2.0, Doubling Maximum Data Rate of Automotive SerDes Interface To Enable Emerging Vehicle Architectures
- MIPI UniPro v2.0 Doubles Peak Data Rate and Delivers Greater Throughput and Reduced Latency for Flash Memory Storage Applications
- MIPI Alliance Opens Access to its MIPI I3C Sensor Interface Specification
- Synopsys Announces Industry's First Verification IP and Test Suites for Latest MIPI CSI-2 v2.0 and PHY Specifications
- MIPI Alliance Introduces a Family of MIPI Gigabit Debug Interface Specifications for Mobile and Mobile-Influenced Designs
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |