Arm and TSMC Demonstrate Industry's First 7nm Arm-based CoWoS Chiplets for High-Performance Computing

Hsinchu, Taiwan R.O.C., September 26, 2019 - Arm and TSMC, the High-Performance Computing (HPC) industry leaders, today announced an industry-first 7nm silicon-proven chiplet system based on multiple Arm® cores and leveraging TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging solution. This single proof-of-concept chiplet system successfully demonstrates the key technologies for building an HPC System-On-Chip (SoC) with Arm-based cores operating at 4GHz in a 7nm FinFET process. The chiplet system also demonstrates for SoC designers an on-die, bi-directional interconnect mesh bus operating at 4GHz, and a chiplet design methodology connected by an 8Gb/s inter-chiplet interconnect over a TSMC CoWoS interposer.

Rather than the traditional SoC approach of combining every system component onto a single die, chiplet designs are optimized for modern HPC processors which partition large multi-core designs into smaller chipsets. This efficient approach enables functions to be split into smaller, separate dies which provide for the flexibility of producing each chiplet on different process technologies, as well as delivering better yields and overall cost effectiveness. And to ensure the highest levels of performance, chiplets must communicate with each other through dense, high-speed, high-bandwidth connections. To address this challenge, this chiplet system features a unique Low-voltage-IN-Package-INterCONnect (LIPINCON^TM) developed by TSMC which has reached data rates of 8Gb/s per pin with excellent power efficiency results.

Chiplet System Details
The chiplet system is comprised of a dual-chiplet CoWoS implemented in 7nm, with each chiplet containing four Arm Cortex®-A72 processors and an on-die interconnect mesh bus. The die-to-die inter-chiplet connection features scalable 0.56pJ/bit (pico-Joules per bit) power efficiency, 1.6Tb/s/mm2 (terabits per second per square millimeter) bandwidth density, and 0.3V LIPINCON low-voltage interface achieving 8GT/s (Giga Transactions per second) and 320GB/s bandwidth. The chiplet system was taped out in December 2018, and produced in April 2019.

“This latest proof-of-concept with our longtime partner TSMC is an excellent foundation for future production-ready infrastructure SoC solutions which will integrate TSMC’s innovative advanced packaging technology with the unmatched flexibility and scalability of the Arm architecture,” said Drew Henry, Senior Vice President and General Manager of Arm’s Infrastructure Line of Business.

“This demonstration chip is an excellent showcase of the system integration capabilities we offer to our customers,” said Dr. Cliff Hou, Vice President of Technology Development for TSMC. “TSMC’s CoWoS advanced packaging technology and LIPINCON inter-chiplet interface enable customers to partition large multi-core designs into smaller chiplets that deliver better yield and better economics. This Arm and TSMC collaboration further unleashes our customers’ innovations in high-performance SoC design for cloud-to-edge infrastructure applications.”

Fig. 1: Dual Chiplet Floorplan

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