IP Controller Core CAN 2.0b and CAN FD of Fraunhofer IPMS certified according to ISO security standard
October 3, 2019 -- Security requirements have grown to meet the same expectations as standard safety equipment featured in motor vehicles. Even lower-priced vehicles today offer driver assistance systems capable of intervening with, for example steering, in certain situations. Fraunhofer IPMS has therefore certified its IP designs, CAN 2.0B and CAN FD Controller Core, for functional safety according to ISO26262:2018. System integrators can now be sure that this IP Core fulfills all criteria of the ASIL B level requirements. On 11. October 2019, Fraunhofer experts will provide more information on diverse automotive IP designs at the GLOBALFOUNDRIES Technology Conference Center in Munich.
Complex electronic systems are at the heart of automobiles today. Dozens if electronic controllers provide functionality, reliability, safety and control systems like driver assistance, ABS, or EPS. ISO 26262 was established in 2011 to increase the safety of such electronic components in motor vehicles. The standard further specified the existing EN 61508 for the development of electronic systems by providing application-specific conditions for the automotive sector. ASICs, FPGAs and SoCs for applications in the automotive sector must now be provided with mechanisms that prevent or control hardware failures. Potential failure types must be listed and evidence that the requirements of one of the four defined levels (ASIL A-D) have been met.
Fraunhofer IPMS has now certified the specially developed CAN controller IP cores (CAN FD and CAN 2.0b) according to the ISO 26262:2018 requirements for the ASIL B level. Developed to network a larger number of control units found in automobiles, the CAN bus is a serial bus system now commonly used in automotive applications. Fraunhofer Group Leader for IP Cores and ASICs, Marcus Pietzsch explains, “System engineers can now use the IP core with certainty, knowing that it can be implemented in security applications that are compliant with ASIL A and ASIL B systems. Fraunhofer IPMS is the first to develop a CAN 2.0b or CAN FD IP design certified according to this standard.”
According to Martin Pietzsch, the design was one of the first CAN IP cores on the market has already been integrated into numerous ASIC and FPGA designs. More than 100 customers have successfully used the IP design. The design is delivered with VHDL or Verilog source code or as a netlist. Fully-synchronous descriptions and modern clock-domain-crossing can be flexibly implemented into individual control devices or switching circuits (System-on-Chip, FPGA) through its 32-bit controller interface (8 Bit and 16 Bit, as well as AMBA APB and AHB options).
Fraunhofer IPMS experts will be providing information of various automotive IP cores at the GLOBALFOUNDRIES Technology Conference to be held in Munich on 11. October 2019. In addition to CAN cores, automotive IP cores such as TSN (Time Sensitive Networking, formerly known as AVB) and LIN will be presented.
|
Related News
- CAN FD Plug Fest Shows Robust Operation of Controller IP Core by CAST and Fraunhofer IPMS
- CAST and Fraunhofer IPMS Introduce CAN XL Bus Controller IP Core
- CAN FD Bus Controller IP Core with ISO and non-ISO Compliance Available Now from CAST
- HighTec C/C++ Compiler Suite Supports Andes' ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications
- CAN FD Controller & LIN 2.1 Controller IP Cores, Available for Immediate Licensing with Proven Automotive Compatibility
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |