Amphion readies hardware accelerator cores

Amphion readies hardware accelerator cores
By Peter Clarke, EE Times
September 4, 2001 (12:46 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010904S0042

BELFAST, Northern Ireland — Amphion Semiconductor Ltd. is preparing to launch several complex cores over the next few weeks, including complete MPEG-2 and MPEG-4 decoders and a turbo-codec circuit suitable for both the wideband-CDMA and cdma2000 versions of third-generation mobile communications.

Illustrative of a new desire to lead rather than follow the semiconductor intellectual-property (IP) market, the Belfast company has also developed reusable microcoded computational engines that include several multiply-accumulators. It will provide protocol stacks and driver software to run on host microprocessors.

The first Amphion microcoded engine is known internally as the SVP, for super vector processor, and is being used in a forthcoming core for a code-excited linear prediction (CELP) voice codec.

A spin-off from Queen's University Belfast and originally named Integrated Silicon Systems, Amphion h as evolved with the semiconductor IP market it serves, said chief executive officer James Doherty.

First-time implementations

"In the past we've provided system-on-chip-style implementations of known algorithms. They're good implementations of Reed-Solomon, Viterbi and so on, but no surprises," Doherty said. "To some extent we were playing catch-up. Now we want to push out ahead and produce first-time implementations of new algorithms."

The company has homed in on broadband, wireless and multimedia applications, where many of the modem and codec functions in which it has specialized are common.

The evolution of semiconductor manufacturing and the accompanying move to higher levels of abstraction is also influencing Amphion's core solutions, Doherty said.

The latest Amphion MPEG cores are intended to run as hardware accelerators alongside microprocessor cores, thereby providing developers with the option of pure software solutions or software-hardware mixes. At the same time, A mphion's hardware solutions are acquiring aspects of programmability.

The forthcoming CELP processor, called CS4220, supports G.729 and G.723.1 standards through the use of the SVP.

"These standards are being applied to voice-over-Internet Protocol today. But they are computationally intensive," said Steve Farson, Amphion's vice president of engineering. "Really, the standards are waiting for the process technology to catch up."

Amphion is providing "a hardware accelerator for the algorithms and up to 64 channels that customers can integrate with a host processor," Farson said. "The microcoded engine is reusable, but only in similar applications. It has ten 16-bit MACs but tailored for the application." The SVP has a gate count of about 220,000 gates.

To help run the CELP, Amphion also provides a software stack for hosting on a microprocessor. "That's a first for us," said Doherty. Amphion has chosen to keep the CELP's interface to the processor very simple — a FIFO memory — to ma ximize its fitness for multiple applications.

The software is provided as C code and early implementations of the CS4220 are being run with ARC Cores' RISC processor and Infineon Technologies' Carmel DSP.

The idea of becoming a provider of hardware accelerators for computationally intensive algorithms is a good fit to the network processor sector of the industry, said Doherty.

Among Amphion's customer base of 125 companies are Broadcom, Cisco Systems, Conexent, Ericsson, Hitachi Semiconductor, Intel, Mitsubishi, NEC and STMicroelectronics. According to Ron Sailors, director of customer marketing at Amphion, an analysis of cores in terms of the time to perform a given function, power consumption and cost usually favors Amphion.

"In performance-cube analysis the smallest cube wins," Sailors said. "Usually we have the smallest cube. If we don't we use it as an incentive to improve."

The company already claims to have the first complete MPEG-2 core that can be contained in a field-programm able gate array. The CS6551 is available for Altera Corp. and Xilinx Inc. FPGAs and operates with H.262-compliant data at 30 Mbits/second for main-profile at main-level performance.

Although a subsequent iteration of the core will be aimed at ASIC-style implementation, Amphion executives said the FPGA implementation was already piquing interest among studio equipment makers that use FPGAs and could see the Amphion-supplied bit stream as a way of providing MPEG-2 decode at little or no extra cost to their equipment. Next will come an MPEG-4 simple-profile video decoder, the CS6750, optimized for low power.

The company plans to demonstrate the MPEG-4 functionality in FPGA. Its launch will be accompanied by disclosure of a two-year road map that shows different cores optimized for studio and advanced real-time versions of MPEG-4.