English
Arm Responds to RISC-V, and More
By Kevin Krewell, EETimes
October 11, 2019
SAN JOSE, Calif. — The big news at Arm Techcon this year is that Arm is opening up its instruction set to customers’ customized instructions for Cortex M cores.
Arm CEO Simon Segars announced the changes in his opening keynote at Arm TechCon. After decades of tight control over the Arm instruction set architecture (ISA), Arm has finally decided that it can allow its licensees to build their own custom instructions, which are often useful to accelerate specialized workloads.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way?
- Arm China's ex-CEO sets up RISC-V company
- Controversial former Arm China CEO founds RISC-V chip startup
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
- Nordic combines Arm and RISC-V for "remarkable" EEMBC benchmarks
Breaking News
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
- MIPI Alliance Announces Board Leadership Appointments
- Alphawave Semi Q4 2024 Trading and Business Update
- ST-GloFo fab plan shelved
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- YorChip announces patent-pending Universal PHY for Open Chiplets