Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing
Cadence VIP with TripleCheck reduces time to market and supports the next-generation NVMe standard
SAN JOSE, Calif. -- Oct 22, 2019 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol. The Cadence® VIP for NVMe 1.4 enables designers to quickly and thoroughly verify their storage, data center and high-performance computing (HPC) system-on-chip (SoC) designs with less effort and a greater assurance that the SoC will meet the protocol standards.
The Cadence VIP for NVMe 1.4 supports the company’s Intelligent System DesignTM strategy, enabling SoC design excellence through best-in-class IP. For more information on the Cadence VIP for NVMe 1.4, please visit www.cadence.com/go/NVMeVIP.
The new Cadence VIP for NVMe 1.4 provides customers with a comprehensive verification solution to develop high-quality NVMe host and device controllers quickly, helping reduce overall time to market. The NVMe 1.4 VIP supports built-in integration with the Cadence VIP for PCI Express® (PCIe®) 5.0 and includes a complete UVM SystemVerilog API for fast integration and SoC-level test creation. Built with Cadence TripleCheck™ technology, customers have access to a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with ready-to-run tests to ensure support for the specification.
“The design team in our company has successfully used the Cadence VIP for NVMe while developing our products for the flash memory controller,” said Mr. Takehiko Tsuchiya, Group Manager, Design Technology Group, Design Technology Innovation Division at KIOXIA Corporation. “The NVMe 1.4 VIP is important for the development of the next generation of our products, supporting the need for a high-performance data interface.”
“The new NVMe 1.4 specification is designed to address the growing needs of enterprise systems that utilize PCIe-based solid-state storage,” said Moshik Rubin, Verification IP Product Management Group Director, System and Verification Group at Cadence. “Cadence is fully dedicated to supporting the latest standard to ensure customers have the tools they need to create differentiated end products. Our release of the first-to-market VIP for NVMe 1.4 is enabling early adopters of the protocol to reduce risk and ensure their designs comply with the specification while achieving the fastest path to IP and SoC verification closure.”
The Cadence VIP for NVMe 1.4 with TripleCheck technology is part of the Cadence Verification Suite and is optimized for Xcelium™ Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies that support the Cadence Intelligent System Design strategy, enabling SoC design excellence.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.
|
Cadence Hot IP
Related News
- Cadence Announces First-to-Market DisplayPort 2.0 Verification IP
- Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
- Synopsys' Complete CCIX IP Solution Enables Cache Coherency for High-Performance Cloud Computing SoCs
- Cadence Enhances RF Verification With High-Performance 'Turbo' Technology and Comprehensive Electromagnetic Analysis
- JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |