EVE reveals hardware-assisted co-modeling product
EVE reveals hardware-assisted co-modeling product
By Michael Santarini, EE Times
January 29, 2002 (2:56 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020129S0038
SAN MATEO, Calif. Paris-based startup Emulation and Verification Engineering (EVE) is introducing its first product: a hardware-assisted co-modeling environment named Zebu that it claims brings the performance of hardware emulation into the software domain at a price of $49,000. The company partially funded by Anvar, the French Agency for the Valorization of Research was started by a group of engineers who left French emulation company Meta Systems, which is now owned by Mentor Graphics Corp. Luc Burgun, former R&D director of Meta Systems, is the president and chief executive officer of the 12-man operation, which until now has done mainly consulting work for the such companies as Ikos and Mentor. EVE's Zebu accelerates the execution of software testbenches via an interface comprising a combination of hardware, firmware and software layers. At the heart of the offering is a PCI card containing a Xilinx Virtex 6000 FPGA and SRAM. Burgun said engineers program their ASIC, intellectual-property or system-on-chip design into the Virtex FPGA using Xilinx's own compilation technology. The Zebu package comes with software running on Linux and soon on Unix that lets engineers connect simulators and instruction set simulators via the SCE-API HDL to the device programmed into the Virtex part. Burgun said the software lets users co-simulate at several MHz in "transaction mode," run cycle-based co-simulation with SystemC and any C/C++ testbenches at 1 MHz, and run co-simulation with VCS, ModelSim and NC-Sim at 50 kHz. The validated blocks can then be combined into a system-on-chip with partitioning software, such as those offered by Synplicity, or can be sent to an emulation system. "The environment can be used from system design all the way through the process," Burgun said. One Zebu card can accommodate up to 600,000 ASIC gates, but a user could plug several cards into a PC to handle larger designs, Burgun said. Emulation vendors are going through a rough period because the price points of their systems are high at a time when customers are cutting their capital-equipment expenditures, Burgun noted. "We are going to sell [our system] for under $50,000. The idea is to sell a lot of systems so that every designer in a design group can use it to validate their own design blocks and IP." Burgun's previous employer, Mentor Graphics' Meta Systems, was banned from selling emulation systems in the United States in the wake of a patent dispute with the System Emulation branch of Cadence Design Systems. Burgun acknowledged that hardware-assisted verification is a contentious and often litigious niche of the EDA arena. In an effort to avoid getting caught up in that environment, he said, his company has applied for several patents on the Zebu technology. The Zebu tool is in beta use now at a few customer sites . EVE plans to introduce the commercial version in May and to show it in March at the DATE conference in Paris.
Related News
- EVE Introduces Next-Generation Hardware-Assisted Verification Platform Series
- Tharas Systems Awarded Key Patents on Hardware-Assisted Verification Technology
- Tharas Systems defines affordable Hardware-Assisted Acceleration for complex System-level verification
- EVE's Hardware-Assisted Verification Platform Accelerates Embedded Software Development for Texas Instruments' OMAP 5 Platform
- EVE Unveils ZeBu-Blade2 Hardware-Assisted Verification Platform
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |