Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
Proposed Working Group established to determine industry interest for a standard to support a functional safety flow
Elk Grove, Calif., October 28, 2019 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Proposed Working Group (PWG) to focus on a standard to enable tool interoperability between Failure Modes, Effects, and Diagnostic Analysis (FMEDA) for functional safety and the design and verification flow of electronic circuits and systems.
“Functional safety is a requirement for safety-critical applications,” stated Lu Dai, Chair of Accellera. “The purpose of the PWG is to explore industry interest and to determine the level of commitment in moving forward with standardization efforts. Our standardization initiatives are user-driven, and we look forward to feedback from the community in the coming months to help us determine our efforts in this area.”
“The EDA industry is already developing tools to perform functional safety analysis and this initiative aims at improving interoperability to capture, propagate, and trace the safety intent and optimizations through an EDA solution and across FMEDA tools,” stated Martin Barnasconi, Accellera Technical Committee Chair. “We invite companies active in this domain to share their best practices, requirements, and expectations on what a functional safety standard should encompass.”
The first Functional Safety Proposed Working Group meeting will be held Friday December 6 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany. The meeting is planned from 10am to 4pm CEST and will include presentations on industry best practices and requirements, and will explore directions for standardization. Attendance is open to everyone, but registration is required. For more information on the Functional Safety PWG, visit here.
Participants in the PWG do not need to be from Accellera member companies.
Background on Functional Safety Proposed Working Group
There is significant activity ongoing in the EDA community to enable functional safety as a part of the design and verification flow. There have been various discussions on the need for a standardized language or format to specify functional safety information and enable tool interoperability. The objective of the PWG is to explore the need for a unified approach to enable a functional safety solution.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org.
|
Related News
- Accellera Forms Functional Safety Working Group to Standardize Data for Interoperability & Traceability in the Functional Safety Lifecycle
- STMicroelectronics, ARM and Cadence Improve Tool and Model Interoperability with Three Joint Contributions to Accellera Systems Initiative
- IAR unveils Functional Safety version of IAR Embedded Workbench for Arm equipped with certified static analysis capabilities
- Arteris Celebrates 3rd Year of Automotive ISO 26262 TCL1 Functional Safety Compliance for Magillem SoC Integration Automation
- Optima Design Automation Announces TUV Certification of its Entire Safety Platform for ISO 26262 ASIL-D Functional Safety Verification
Breaking News
- Vertex Growth commits €10M in Dolphin Semiconductor
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
- Doteck Integrates intoPIX JPEG XS for High-Performance ST 2110 8K & 4K Encoding
- Gartner Says Worldwide Semiconductor Revenue Grew 21% in 2024
- eDP/DP 1.4 Tx PHY & Controller IP Cores Now Available to Meet Rising Demand for High-Performance Display Solutions with Next-Gen Visual Connectivity
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |