Rambus Announces Comprehensive PCI Express 5.0 Interface Solution
SUNNYVALE, Calif. – Nov. 12, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it now offers a comprehensive and optimized interface solution designed for PCI Express (PCIe) 5.0, with backward compatibility to PCIe 4.0, 3.0 and 2.0. The Rambus PCIe 5.0 interface solution includes both PHY and digital controller for easy SoC integration and faster time to market. With the PHY designed for an advanced 7nm process node, the integrated solution offers best-in-class power, performance and area thanks to the industry-proven engineering and signal integrity expertise of Rambus.
“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, HPC, storage and networking,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.”
In addition to the state-of-the-art PHY, the Rambus PCIe 5.0 solution includes a high-performance, digital controller core from recently acquired Northwest Logic. The Rambus PHY and controller are offered as a fully validated and integrated solution, or they can be licensed separately and used with third-party solutions. The entire solution is backed by Rambus design, integration and support services for first-time customer success.
PCIe 5.0 Interface Subsystem Example
Benefits of Rambus PCIe 5.0 Solution
- Integrated and co-validated PHY and digital controller for complete interface solution
- Built with Rambus’ industry-proven design methodology for long-reach PCIe interfaces
- 32 GT/s bandwidth per lane with 128 GB/s bandwidth in x16 configuration
- Backward compatible to PCIe 4.0, 3.0 and 2.0
- PHY Supports Compute Express Link interconnect
- Advanced multi-tap transceiver and receiver equalization compensate for more than 36dB of insertion loss
- Best-in-class power, performance and area
- Supports performance-intensive applications including AI, data center, HPC, storage and 400GbE networking
Availability and Additional Information
The new Rambus PCIe 5.0 solution is available worldwide in an advanced 7nm FinFET process.
For more information on our complete family of SerDes solutions, please visit rambus.com/serdes.
|
Related News
- Mobiveil, Inc. today announced availability of its PCI Express 5 controller IP
- Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP
- Synopsys DesignWare IP for 5.0 Gbps PCI Express Enables First-Pass Silicon Success for PMC-Sierra's High-Performance SoC
- Rambus Showcases Silicon Verified Demo Compliant with Gen2 Revision 0.5 Specification for PCI Express
- Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |