Mixel Announces Immediate Availability of MIPI D-PHY v2.5 IP
Mixel first to support D-PHY v2.5 up to 18Gbps aggregate data rate
SAN JOSE, Calif.-- December 3, 2019 -- Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that its MIPI® D-PHYSM IP compliant to MIPI D-PHY v2.5 specification is now available. MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2SM), as well as Display Serial Interface (DSISM) and DSI-2SM. The MIPI D-PHY v2.5 specification was recently adopted by the MIPI Alliance in October 2019 and Mixel is the first IP provider to make this IP available to its customers.
Mixel’s MIPI D-PHY v2.5 IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI master or MIPI slave, support camera interface CSI-2 v3.0 and display interface DSI-2 v1.1 and is backwards compatible with previous generations of each specification.
Mixel D-PHY v2.5 supports speeds up to 4.5Gbps per lane, an aggregate data rate of 18Gbps. It supports all v2.5 features not available in previous versions of the specifications such as Spread Spectrum Clocking (SSC) and transmit equalization (de-emphasis). It also supports new power saving functionality such as HS-TX half swing mode and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround.
"As SoC design requirements become more complex and require higher bandwidth, D-PHY v2.5 fulfills a need in the mobile and mobile-influenced markets such as automotive, and IoT, among others,” said Joel Huloux, MIPI Alliance chairman. “By introducing the D-PHY v2.5 IP solution to the industry, Mixel is advancing the capabilities of SoC designers and strengthening the MIPI ecosystem.”
Mixel’s D-PHY IP has been silicon-proven in 9 different nodes at 8 different foundries in multiple configurations including a patented RX+ configuration that allows for full-speed, in-system production testing with minimal overhead.
“We are excited to announce the immediate availability of Mixel’s D-PHY v2.5 IP, particularly because the v2.5 was just adopted by the MIPI Alliance very recently,” said Ashraf Takla, President and CEO of Mixel. “This further demonstrates our continued commitment to our customers and the MIPI ecosystem by providing another industry first.”
Mixel will be attending IQPC: Semiconductor Applications for ISO 26262 in Munich, Germany, on December 2-5, presenting a technical paper covering the development and certification of Mixel’s Mixed-Signal PHY IP for ISO 26262 functional safety and showcasing many of its own and its customers’ products.
Availability:
Mixel D-PHY v2.5 IP is available now.
Additional Resources:
For more information on Mixel’s IP portfolio, please visit https://mixel.com/ip-cores.
About Mixel:
Mixel is a leading provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHYSM, MIPI M-PHY®, MIPI C-PHYSM, LVDS, and many dual mode PHY supporting multiple standards. Mixel was founded in 1998 and is headquartered in San Jose, CA, with global operation to support a worldwide customer base. For more information contact Mixel at info@mixel.com or visit www.mixel.com .
About MIPI Alliance:
MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone manufactured today. Founded in 2003, the organization has over 300 member companies worldwide and 14 active working groups delivering specifications within the mobile ecosystem. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP tool providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit www.mipi.org.
|
Mixel, Inc. Hot IP
Related News
- Mixel Announces Immediate Availability of MIPI C-PHY/D-PHY Combo IP on STMicroelectronics 40LP Process Technology
- T2M-IP Unveils MIPI D-PHY v2.5 Tx and DSI Tx Controller v1.2: Silicon-Proven, Low-Power, Cost-Effective IP Core Solutions for Advanced SoCs
- T2M-IP Announces Silicon-Proven MIPI D-PHY v2.5 Tx and DSI-2 Tx Controller Low-Power, Cost-Effective IP Cores Solutions for Advanced SoCs
- Arasan announces the immediate availability of its 2nd Generation MIPI D-PHY for GlobalFoundries 22nm SoC Designs
- Arasan announces the immediate availability of its ultra-low power MIPI D-PHY IP for the GlobalFoundries 12nm FinFET process node
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |