SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit
VIP Ensures Thorough, Seamless Coverage-Driven Verification Flow Between Simulation, Emulation, Formal Verification
SAN JOSE, CALIF –– December 3, 2019 ––
WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification and Design Intellectual Property (IP)
WHAT: Will highlight new additions to its extensive and broad portfolio of VIP that support TileLink, the chip-scale interconnect standard, and the Verilator open-source hardware description language (HDL) simulator at the RISC-V Summit. It will offer demonstrations of its Smart ViPDebug™, a visual protocol debugger that reduces debug time.
WHEN: Tuesday, December 10, from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m.
WHERE: San Jose Convention Center, San Jose, Calif.
Attendees can schedule Smart ViPDebug demos or meetings to learn how SmartDV’s VIP ensures a thorough and seamless coverage-driven verification flow with no coverage gaps between simulation, emulation or formal verification at demo@smart-dv.com.
About SmartDV
SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Design and Verification IP supports simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, RISC-V verification services. The result is Proven and Trusted Design and Verification IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more.
|
SmartDV Technologies Hot IP
SmartDV Technologies Hot Verification IP
Related News
- NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
- SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
- SmartDV Supports RISC-V Movement with TileLink Verification IP for RISC-V Based Systems
- StarFive's RISC-V based JH-7110 intelligent vision processing platform adopted VeriSilicon's Display Processor IP
- Learn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation's Presentations at the 2020 RISC-V Summit
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |