Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs
SAN JOSE, Calif., 09 Dec 2019 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications. Through use of the Cadence Innovus™ Implementation System and the Voltus™ IC Power Integrity Solution, GUC achieved first-pass silicon success and met its GHz performance target for its multi-billion gate designs. For more information on the Cadence digital and signoff flow, please visit www.cadence.com/go/dsfcspr.
Traditional digital implementation and signoff tools lack the capacity GUC required for their multi-billion gate designs during the implementation and signoff stages. Alternative solutions on the market must be greatly scripted because they don’t offer a shared data model-level integration, requiring more manual work with increased design margins and limited performance. Where the traditional tools fall short, the tightly integrated Cadence solution helped GUC meet power, performance and area (PPA) targets and deliver their large-capacity, advanced designs on time.
The Innovus Implementation System improved the GUC design team’s productivity through its efficient hierarchical partitioning flow, advanced top-level floorplanning and block implementation and closure capabilities. The Voltus IC Power Integrity Solution enabled GUC to accurately analyze the top-level full-chip static/dynamic power, IR drop and electro-migration through its distributed processing capability using innovative extensive parallelism technology. The seamless shared data model-level integration between the Cadence tools provides GUC with an efficient way to close signoff EM-IR issues during block implementation, reducing costly iterations and engineering change orders (ECOs).
“As a leader in ASIC design, we need to deliver highly complex designs to customers quickly, particularly for emerging application areas like AI and HPC,” said Louis Lin, senior vice president of Design Services at GUC. “Through our deep collaboration with Cadence, we deployed their digital implementation and signoff tools quickly and easily, and the Cadence team also provided prompt support to further optimize our delivery cycle time and achieve our PPA targets.”
The Cadence Innovus Implementation System and Voltus IC Power Integrity Solution are part of the broader digital implementation and signoff full flow and provide customers with a faster path to design closure. The tools in the flow support the company’s Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence for AI and HPC applications.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
|
Cadence Hot IP
Related News
- Global Unichip Corporation Uses Cadence Encounter Digital Implementation System to Complete Its First Production Design on TSMC 16FF+ Process
- Brite Semiconductor Improves Quality of Results and Reduces Time to Market for Four SoC Designs with Cadence Digital Implementation and Signoff Tools
- Cadence Low-Power, Advanced-Node Digital Technology Incorporated Into SMIC 40nm Reference Flow
- Global Unichip Collaborates With Cadence and Kilopass to Deliver Innovative Consumer Entertainment Designs
- TSMC and Cadence Collaborate to Deliver AI-Driven Advanced-Node Design Flows, Silicon-Proven IP and 3D-IC Solutions
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |