AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding
University of Southampton Spin-Out Unveils Breakthrough 5G Cellular Optimisation Technology Delivering Highest Throughput, Lowest Latency Forward Error Correction IP
Southampton, UK – 11th December 2019: AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, announced today the launch and general availability of the 5G NR LDPC version of its error correction IP, which reduces latency up to 16x to support numerology 4 in 3GPP 38.211 and also results in significant power savings for mobile networks with lower order numerology networks. The company’s LDPC IP is optimized and configurable to support high performance base station solutions or low power (small size) mobile terminal solutions.
Channel coding, also known as forward error correction, is used to correct transmission errors in mobile communications caused by noise, interference and poor signal strength. This announcement reflects a dramatic change in the direction of coding in mobile communications standards. While 3G and 4G used Convolutional and Turbo codes for the control and data channels, 5G uses the much more sophisticated Polar and LDPC codes, and requires the industry to look afresh at how to address error correction. If channel coding is not working well the impact on mobile networks is poor capacity, poor data rates, poor coverage and poor quality of service. AccelerComm’s LDPC IP brings many years of experience in error correction to address this challenge in the 5G networks now being launched.
AccelerComm CEO, Tom Cronk, commented: “For all the hype around 5G, the simple fact is ‘ping time’ remains an issue, stifling new revenue opportunities for operators from services such as gaming or VR before they’ve had an opportunity to monetise them. After more than 15 years of research by the team, first at the University of Southampton and now at AccelerComm, we’re able to deliver on the 5G promise of a low latency, high throughput experience.”
The LDPC IP is fully compliant with the 3GPP NR standard for PDSCH, PUSCH and also supports the full range of uncoded and encoded block sizes. It implements the entire LDPC encoding and decoding chain in 3GPP TS38.212 with superior error correction performance and hardware efficiency. It also tightly integrates the components in the chain to reduce hardware usage and latency and boasts a simple interface, making it quick to integrate.
The solutions provided by AccelerComm enable all 5G NR channels to be coded. AccelerComm solutions are 3GPP standards compliant and cover the total processing chain, including the encode-decode engine, channel interleaving, rate matching, CRC and early termination functions.
About AccelerComm
AccelerComm is the company supercharging 5G with Optimisation and Latency Reduction IP. It provides LDPC, polar and turbo FEC solutions which enable optimal performance of communication systems and solves the challenges that would otherwise limit the speed of 5G, namely the error correction decoding that is required to overcome the effects of noise, interference and poor signal strength. For more information please visit: www.accelercomm.com
|
AccelerComm Limited Hot IP
Related News
- AccelerComm introduces software only 5G NR channel coding IP at MWC Barcelona 2019
- AccelerComm introduces improved channel equalisation for 5G NR at MWC Barcelona 2020
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
- AccelerComm Launches PUSCH Channel Simulator for 5G L1 Performance Evaluation
- AccelerComm Expands LDPC Accelerator IP Licenses for 5G Cloud RAN High-Capacity Solutions
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |