NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm)
Enflame Technology Selects Rambus HBM2 Memory Subsystem Solution For Next-Generation AI Training Chip
SUNNYVALE, Calif. – Dec. 11, 2019 – Rambus Inc. (NASDAQ: RMBS) a premier silicon IP and chip provider making data faster and safer, today announced that Enflame (Suiyuan) Technology has selected Rambus HBM2 PHY and Memory Controller IP for its next-generation AI training chip. Rambus memory interface IP enables the development of high-performance, next-generation hardware for leading-edge AI applications.
“Artificial intelligence training requires far greater memory bandwidth than standard compute applications. Rambus’ proven HBM2 memory subsystem IP delivers the ultra-high bandwidth performance our AI chips need,” said Arthur Zhang, COO of Enflame Technology. “Using Rambus interface IP cores, we are revolutionizing what’s possible in AI technology.”
Related |
HBM2/2E Memory Controller Core ![]() |
Optimized for low-latency and high-bandwidth memory applications, the Rambus HBM2 interface solution delivers maximum performance and flexibility in minimal form factor and power envelope. The comprehensive HBM2 subsystem solution of PHY and memory controller provides 2Tb/s of bandwidth, making it the perfect fit for Enflame Technology’s cloud AI training needs. Complementing this interface IP, Rambus provides silicon interposer and package reference designs, and supports signal and power integrity (SI/PI) analysis.
“Enflame Technology’s repeat choice of Rambus showcases our HBM2 PHY and memory controller IP as the ideal solution for complex neural network-based AI and machine learning chips,” said Hemant Dhulla, vice president and general manager of IP Cores at Rambus. “Our HBM portfolio of solutions already in volume production deliver the memory performance needed at the frontier of AI computing.”
For more information on Rambus HBM2 PHY offerings, please visit https://www.rambus.com/interface-ip/ddrn-phys/hbm/. Find out more details on Rambus Memory Controllers at https://www.rambus.com/interface-ip/controllers/memory-controllers/.
|
Search Silicon IP
Related News
- Rambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads
- Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem
- Ferroelectric Memory GmbH (FMC) Raises $20 Million to Accelerate Next-Generation Memory for AI, IoT, Edge Computing, and Data Center Applications
- Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies
- Rambus Unveils Mobile XDR Memory for Next-Generation Mobile Products
Breaking News
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Siemens acquires Altair to create most complete AI-powered portfolio of industrial software
- Alphawave Semi Reveals Suite of Optoelectronics Silicon Products addressing Hyperscaler Datacenter and AI Interconnect Market
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |