Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation
Henderson NV, USA – January 28, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that Cobham Gaisler has successfully verified its first RISC-V line of processors, called NOEL-V™, using Riviera-PRO™ for mixed-HDL simulation.
NOEL-V is a synthesizable VHDL model of a 64-bit processor that implements the RISC-V architecture, with an advanced 7-stage dual-issue in-order pipeline and provides up to 4.69 CoreMark/MHz. “As a leading vendor of space-grade microprocessors, we needed to verify NOEL-V using a reliable and high-performance RTL simulator with advanced debugging and DRC checking capabilities”, said Jan Andersson, Director of Engineering at Cobham Gaisler. “We used Riviera-PRO for functional, gate-level and timing simulation and we were very pleased with its rich VHDL support, compile and simulation speed.”
“Because of its open-source model, RISC-V is a game-changing technology for hardware that spans across various embedded applications including space and mission-critical”, said Louie De Luna, Director of Marketing at Aldec. “We’re excited to help and work with Cobham Gaisler, and we look forward to solving new verification challenges for the future generations of NOEL-V.”
About Cobham Gaisler
Cobham Gaisler provides IP cores and supporting development tools for embedded processors based on the SPARC and RISC-V architectures. Cobham Gaisler has a long experience in the management of ASIC development projects, and in the design of flight quality microelectronic devices. The company specializes in digital hardware design (ASIC/FPGA) for both commercial and aerospace applications. http://www.cobham.com/gaisler
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
|
Related News
- Cobham Advanced Electronic Solutions Introduces Support for Wind River VxWorks RTOS for NOEL-V Processor
- Cobham Gaisler and fentISS Deepen Collaboration around RISC-V
- Porting PikeOS to NOEL-V and LEON: SYSGO and Cobham Gaisler Extend Cooperation around RISC-V
- CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical Infrastructure
- Fractile Licenses Andes Technology's RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |