Arasan Announces immediate availability of its SUREBOOT xSPI Host IP
Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its xSPI Host IP Core supporting the JEDEC JESD251 specification.
Feb 24, 2020, San Jose, CA -- Arasan expands its solid state storage IP portfolio with the announcement of the immediate availability of its eXpanded Serial Peripheral Interface (xSPI) IP compliant to the JEDEC JESD251 xSPI Specification V1.0. The xSPI IP also supports JESD216D Serial Flash Discoverable Parameters (SFDP). The JEDEC JESD251 standardizes the NOR Flash Device Interfaces.
Related |
xSPI Master IP | NOR IP |
Arasan’s xSPI IP is a universal NOR Flash Interface IP with support for Octal SPI, QSPI, Dual SPI and SPI Interfaces. Arasan, with its leadership in memory interface IP understands that SoC’s will boot up directly from the NOR FLASH and reliability of the xSPI interface with regard to compliance and fail safe performance is mandatory. Arasan’s xSPI IP has undergone rigorous testing at the RTL level with its own test environment and 3’rd party VIP. The IP has also been tested on FPGA with xSPI Flash Memory devices.
Arasan provides a Total xSPI IP Solution with software, FPGA prototyping platform and 3’rd party UVM based VIP in addition to the Verilog RTL code and test environment.
Arasan xSPI IP joins its comprehensive portfolio of solid state storage IP which includes UFS + M-PHY IP, eMMC IP, SD Card Host IP + SD UHS-II IP and ONFI NAND Flash IP + ONFI PHY IP.
Availability
The Arasan xSPI Host IP is available immediately for ASIC and FPGA applications. Arasan is a member of both Xilinx, Intel and Microsemi FPGA IP Partner Programs.
About Arasan
Arasan Chip Systems, a JEDEC member is a leading provider of IP for mobile storage and mobile connectivity interfaces. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP, AMS PHY IP, Verification IP, HDK and Software. Arasan has a focused product portfolio targeting mobile SoC’s. The term Mobile has evolved over our two decade history to include all things mobile – starting with PDA’s in the mid 90’s to Smartphones & Tablets of the 2000’s to today’s Automobiles, Drones and IoT’s. Arasan is at the forefront of this evolution of “Mobile” with its standards-based IP at the heart of Mobile SoC’s.
Over a billion chips have been shipped with Arasan IP including all of the top 10 semiconductor companies.
|
Arasan Chip Systems Hot IP
Related News
- Arasan Announces immediate availability of its SUREBOOTâ„¢ Total xSPI PHY IP
- Arasan Announces immediate availability of its I3C Host / Device Dual Role Controller IP
- Arasan announces the immediate availability of its 2nd Generation MIPI D-PHY for GlobalFoundries 22nm SoC Designs
- Arasan announces the immediate availability of its MIPI D-PHY IP as Tx Only or Rx Only for the GlobalFoundries 12nm FinFET process node
- Arasan announces the immediate availability of its ultra-low power MIPI D-PHY IP for the GlobalFoundries 12nm FinFET process node
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |