DAeRT: eInfochips' DFT Framework that Increases Productivity and Reduces Silicon Development Cycle

eInfochips launches DAeRT (DFT Automated Execution and Reporting Tool) - an automated framework for the semiconductor industry, which provides a complete solution for DFT, starting from architecture to implementation for any ASIC (Application Specific Integrated Circuit).

San Jose, California -- March 16, 2020 – eInfochips (an Arrow Company) today announced it has built a proven framework for implementing DFT architecture for ASIC, which enables ~100% testability for ASIC designs. It supports various DFT methodologies starting with iJTAG/JTAG, MBIST, scan, ATPG, pattern validation, test-timing analysis, and post-silicon validation. It also supports Synthesis.

DAeRT is the result of eInfochips’ over two decades of experience in the DFT field. DAeRT gives flexibility to your flow based on GUI/non-GUI, to be filled with respective variables and it can take care of the entire execution of a specific stage. The DAeRT framework is part of the eInfochips DFT solution that includes MBIST, scan, iJTAG/JTAG, ATPG, and post-simulation, which helps to identify if any existing manufacturing defect exists after the fabrication of an SoC/ASIC.

With the increasing complexity of designs and with growing competition, chip designers face an increasing amount of pressure to reduce the time-to-market for chips while ensuring the chips function as intended. The DAeRT framework provides a platform for the designers to ensure that the implementation is done with high quality, because of the rigorous reviewing done by the framework at each stage, and with high automation, the time needed to implement also reduces exponentially.

"As a leading global service provider in the semiconductor industry, eInfochips makes significant investments in developing a robust framework called DAeRT which offers high automation flow while maintaining the strict quality of SoC," said Nirav Nanavati, Delivery Manager-ASIC who defines the overall architecture of the DAeRT. Besides, this framework helps to define the DFT architecture in such a way that it can reduce the shift power consumption by at least 10% and improve overall schedule by 5% for any project in the semiconductor industry, said by Mr. Saumil Modi – key developer of the framework & DFT architecture expert, working as a Technical Lead in eInfochips.

There are many benefits of this framework, some of them are mentioned are below:

DAeRT Benefits

Complete automation for DFT implementation
User-friendly graphical user interface
Support various EDA tools for DFT implementation and can easily enhance any other tools
Very helpful to achieve your targeted coverage goals for stuck-at and transition-delay faults
Improve overall DFT implementation schedule cycle by 20%

Availability & Resources

The DAeRT framework is available now.

For more information, visit https://www.einfochips.com/ips-frameworks/dft-automated-execution-and-reporting-tool/

About DAeRT Framework

The DAeRT framework includes all the major stages for implementing DFT logic in the design and guarantees high-end implementation with reduced implementation time. To accelerate implementation, it provides a makefile based environment, which simplifies the implementation of test logic in designs. eInfochips’ extensive investment in developing a high-quality, robust framework will enable DFT engineers to reduce the time for implementation and improve the quality of tasks by rigorous checking and reviewing of each stage.

About eInfochips

eInfochips is a leading service provider for product engineering services and semiconductor industry of high-quality, DFT IP solutions for SoC designs. Of the multiple domains served by eInfochips, semiconductor services are a prevalent domain. eInfochips provides turnkey services starting from Design till GDS-II. eInfochips is one of the first service providing companies to tape-out multiple SoCs on 16nm as well as 7nm technology.