RT-660-FPGA DPA-Resistant Hardware Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140
TriCN to preview next-generation, all-digital Serdes "engine" at DesignCon 2003
New TriDL G2 Technology Delivers Up to 5 Gigabit/second Throughput in Support of Maximum Performance for PCI Express and XAUI Multi-Gigabit Interfaces
SAN FRANCISCO, CA –January 27, 2003 –TriCN, a leading developer of intellectual property (IP) for high-speed interface technology, today announced the introduction of its groundbreaking Serializer/Deserializer [SerDes] technology, named TriDL G2 (Digital Dynamic Deskewing Link). TriDL G2 is an ultra high-performance I/O interface "engine" that is capable of delivering up to 5 Gigabit/second throughput with significantly lower power and area requirements than comparable analog solutions. The TriDL G2 SerDes will serve as the core, underlying technology for TriCN's upcoming introduction of PCI Express and XAUI interface products.
"TriDL's all-digital implementation is a dramatic departure from the competition", explains Ron Nikel, Chief Technology Officer with TriCN. "The all-digital approach not only provides savings in area and power usage, but also streamlines porting and testability, and offers increased noise immunity not found in analog based devices. This is a powerful and unique combination of features that will be extremely attractive to designers of high performance semiconductors used in communications, networking, data storage and memory markets."
The TriDL G2 architecture consists of a transmitter hard macro, and a receiver hard macro. The modular design of the TriDL G2 SerDes allows semiconductor developers to integrate the TriDL G2 SerDes IP in bundles of 1 to 32 lanes, yielding as much as 320 Gb/s aggregate data rates, sufficient to meet even the most aggressive throughput requirements.
TriDL G2 employs TriCN's unique, patent-pending approach to skew compensation, for maximum skew tolerance and unprecedented throughput levels. Offering a dynamic alignment approach to skew compensation, it provides bit-level de-skewing that delivers up to 24UI of skew compensation at 5Gb/s per lane. This is performed without the use of a delay-locked loop (DLL), thereby affording semiconductor designers significant savings in silicon area over comparable analog DLL-based implementations. Area requirements for TriDL G2 are .12mm² per lane.
By eliminating the need for a DLL, TriDL G2 also functions with dramatically lower power requirements compared to analog solutions. Typical combined power requirements for TriDL G2's transmitter and receiver are 24 mW per lane.
Availability
TriCN's TriDL G2 has been targeted for Taiwan Semiconductor Manufacturing Company's (TSMC) 0.13um process, and will be made available in conjunction with the introduction of TriCN's PCI Express and XAUI products beginning inQ2 of 2003.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. This IP is designed for IC developers addressing bandwidth-intensive applications, in the communications, networking, data storage, and memory space. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, MIPS Technologies, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.
For more information, please visit TriCN's web site at www.tricn.com.
TriCN: The Single Source for Interface IP™
|
Related News
- Digital Core Design Unveils DPSI5 - The Next-Generation IP Core for PSI5 Communication
- RIKEN adopts Siemens' emulation and High-Level Synthesis platforms for next-generation AI device research
- DMP Released Next-Generation AI Accelerator IP "ZIA A3000 V2" - Industry-leading PPA efficiency to propel the future of edge AI
- Preferred Networks Inc. adopts Siemens' PowerPro software for next-generation AI chip design
- ADTechnology announces next-generation platform "ADP600" at Samsung Foundry Forum 2024
Breaking News
- Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
- Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution
- S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development
- PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
Most Popular
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- Cadence to Acquire Arm Artisan Foundation IP Business
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New Breakthroughs in China's RISC-V Chip Industry
- Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |