Inomize Selects Synopsys' Silicon-Proven 56G Ethernet PHY IP for High-Performance Computing and Communications SoC Design
DesignWare 56G PHY Delivers Leading Power and Performance with High Reliability
MOUNTAIN VIEW, Calif., March 19, 2020-- Synopsys, Inc. (Nasdaq: SNPS) today announced that Inomize selected its silicon-proven DesignWare® 56G Ethernet PHY IP to accelerate development of Inomize's high-performance computing, software-defined radio (SDR), and power-efficient communications System-on-Chip (SoC). After evaluating other solutions in the market, Inomize chose Synopsys' DesignWare 56G Ethernet PHY IP due to its unique transmitter and receiver architecture for the best power, area and performance tradeoffs. In addition, Synopsys' 56G Ethernet PHY delivered high reliability across a wide range of temperature, process, and voltage variations, which was key to helping Inomize ensure robust operation in harsh conditions. Inomize leveraged Synopsys' 56G Ethernet PHY's comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast integration of the IP into their SoC. The DesignWare 56G Ethernet PHY IP is part of Synopsys' comprehensive solution for high-performance cloud computing and networking SoCs including DesignWare 112G Ethernet, Die-to-Die, PCI Express 5.0, HBM2/2E, and DDR5/4 IP.
"As a leading ASIC design firm, Inomize is committed to delivering high-quality solutions that address our customer's most complex design requirements across a range of applications," said Udi Shaked, CEO at Inomize. "For our latest advanced SDR communications SoC, we required a high-performance 56G Ethernet PHY that met our stringent power, area, performance and reliability needs. After an extensive evaluation process, we chose Synopsys. As a trusted IP provider, Synopsys met all of our technical requirements and gave us confidence we would be successful with our design."
"Synopsys makes significant investments in providing our customers with a broad portfolio of highly differentiated IP that leads in power, performance and area to address critical application requirements," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Our silicon-proven DesignWare 56G Ethernet PHY IP combined with our unmatched quality, support, and engineering expertise enables customers like Inomize to lower their integration risk and speed time to market."
Availability
The DesignWare 56G Ethernet PHY is available now in 16-/12-nm and 7-nm FinFET processes.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enable designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Chelsio Adopts Synopsys DesignWare 56G Ethernet PHY IP to Accelerate Development of High-Performance Computing SoC
- Synopsys' Silicon-Proven DesignWare DDR IP for High-Performance Cloud Computing Networking Chips Selected by NVIDIA
- Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs
- Synopsys Accelerates High-Performance Computing SoC Designs with Industry's Broadest IP Portfolio for TSMC's 5nm Process Technology
- Synopsys Targets 400G Hyperscale Data Centers with High-Performance Ethernet IP
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |