PLDA Announce Complete Support for CXL and Gen-Z protocols

Following the recent Announcement of MoU between the CXL Consortium™ and the Gen-Z Consortium™, PLDA Launches their XpressLINK™ CXL IP, providing an immediate Compute Express Link solution for SoC developers

May 4, 2020 -- PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today reaffirms its support for both CXL™ and Gen-Z™ protocols with its newly-launched XpressLINK™ CXL Controller IP and its upcoming Gen-Z Controller IP. Today’s announcement builds on an April 2, 2020 announcement from the Compute Express Link Consortium™ and Gen-Z Consortium highlighting their execution of a Memorandum of Understanding (MoU) for collaboration between the two organizations. PLDA is now perfectly positioned within the IP arena to provide both CXL and Gen-Z technologies to designers in the semiconductor space, including in datacenter, storage, compute, AI, and networking industries.

The Memorandum of Understanding (MoU) announced earlier this month between the CXL Consortium and the Gen-Z Consortium, has clarified the ways that CXL and Gen-Z can create best-in-class solutions now and into the future. CXL and Gen-Z are complementary high speed interconnect protocols, with CXL enabling cache coherent node-level computing and Gen-Z focusing on fabric connectivity at the rack and row level. PLDA’s announcement of their XpressLINK CXL IP combined with their upcoming Gen-Z IP furthers the aims outlined in the MoU announcement and ensures early adopters have the opportunity to integrate these solutions seamlessly into their designs. PLDA remains committed to both protocols and is actively participating in various workgroups to accelerate adoption and ensure interoperability.

About PLDA’s XpressLINK CXL IP

PLDA’s newly announced XpressLINK CXL IP is a parameterizable Compute Express Link (CXL) Soft IP controller designed for both ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA's silicon-proven XpressRICH™ Controller for PCIe 5.0 architecture for CXL.io, and adds CXL.cache and CXL.mem specific to CXL.

Key highlights of XpressLINK’s CXL IP include:

Support for the CXL 2.0 specification
Implementation of the CXL.io, CXL.mem, and CXL.cache protocols
Support for all 3 defined CXL device types
Support for the PCI Express 5.0 Base Specification, Revision 1.0
Support for the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface width

According to Arnaud Schleich, CEO of PLDA “The announcement of the MoU between the CXL and GenZ Consortiums is a key event in the IP Market as it paves the way to the future architecture of high speed interfaces. As an historic actor in this Industry, it was logical for PLDA to expand its product line to include both protocols and we are proud to be committed to pushing this evolution to the next level.”

“CXL and Gen-Z technologies are extremely complementary and will allow secure sharing of highly utilized, performance sensitive components used by multiple workloads,” said Gen-Z Consortium President Kurtis Bowman. “The delivery of solutions for both interconnect protocols from companies such as PLDA will be critical to driving innovation.”

“We anticipate the combined solution of Gen-Z and CXL technologies will enable important advances in Storage, Datacenter, AI, and Networking design. To achieve these milestones, we will continue to rely on our working group members such as PLDA to create easy-to-integrate solutions,” said Jim Pappas, Board Chair, CXL Consortium.

More information:

You can access more information on PLDA’s CXL and Gen-Z Solutions as follows: