VSIA ponders standards for software reuse
VSIA ponders standards for software reuse
By Ron Wilson, EE Times
February 1, 2002 (1:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020129S0045
SANTA CLARA, Calif. The Virtual Socket Interface Alliance (VSIA) debated the wisdom of turning its attention toward the reusability of software in a panel discussion Monday (Jan. 28). The organization has heretofore focused exclusively on improving the reusability of hardware intellectual property in system-on-chip designs. But SoCs are increasingly focused on software, not just hardware, said Michael Kaskowitz, vice president and general manager of the Embedded Systems Division of Mentor Graphics Corp., in a keynote prior to the panel. And the lack of standards in all areas of software module development, from basic definition of terms to debug capabilities, greatly harms the efficiency of software development, he argued. This is particularly the case for what Kaskowitz called hardware-dependent software code whose structure and function is determined by the hardware implementation of the SoC in which it will execute. Kaskowitz called for the VSIA to extend its charter into this new realm. "Getting acceptance of hardware-dependent software standards should be easy compared to hardware standards," he said. "Hardware developers tend to be invested in their particular approach to hardware interoperability, but they regard software as a necessary evil." Differences dissolve After being introduced by VSIA vice president of marketing Larry Cooke, the panel presented several divergent views on the subject. This writer provided some market data based on an Integrated System Design survey, stating that about half of SoC hardware designers appear to be involved in software development, and an even larger portion are involved in hardware/software co-verification. Further, many of these designers create not just hardware-dependent software by VSIA's definition, but also application software. Cadence Labs (Berkeley, Calif.) fellow Grant Martin then suggested that both a traditional, CPU-centric embedded systems de sign style and a new platform-based methodology coexist in the SoC world, and that the industry needs a forum in which to address reuse of code in both design styles. Ian Phillips, principal staff engineer at ARM Ltd. (Cambridge, United Kingdom), took a contrary view. Arguing from a hardware designer's perspective, he said, "This house is built on sand, and we need to make it firm." While IP reuse has helped reduce design risks, Phillips said there are many more issues in the hardware realm that have not been addressed, including standard ways of interconnecting IP blocks, standardization of design rules and physical data formats. Presenting a third viewpoint, Brian Bailey, chief technologist at Mentor Graphics Consulting, claimed that panelists were only looking at trees, not at the forest, of system design. "Hardware-software co-design is probably the least important aspect of system design in the larger scheme of things," he said. As an example, he cited the notion of encapsulation, common in the object-based software design world but still nearly unexplored in the hardware realm. "There is a lot more to be done on all parts of the system design problem," he concluded. Ron Wilson is editorial director of Integrated System Design, a sister publication of EE Times.
Related News
- VSIA may widen charter to software reuse standards
- VSIA takes hard look at embedded software reuse
- Intento Enters EDA Market with Software that Accelerates Analog and Mixed-Signal Design, Enables IP Re-Use Through Technology Migration
- Software Development: Not Written Here Is New Norm
- Magillem promotes IP Reuse, interoperability through IEEE 1685 and launches its IP-XACT Checkers Suite Software and Compliance Lab
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |