Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores
Munich, Germany – June 2nd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, announced today that the Codasip SweRV Support Package has been extended to include the open source, RISC-V-based SweRV Core™ EH2 and EL2 that were contributed to CHIPS Alliance by Western Digital. These have been added to the support already released for the SweRV Core EH1.
The SweRV cores EH2 and EL2 are available to the open-source community through CHIPS Alliance, an open-source development organization which seeks to provide a barrier-free environment to allow collaboration for open-source software and hardware code. The rapid inclusion of EH2 and EL2 in the Codasip SweRV Support Package after their release by CHIPS Alliance was enabled by the close cooperation of Codasip and Western Digital RISC-V teams.
The SweRV Core EH2 is a high-performance 32-bit, dual-thread, superscalar, 9-stage pipeline core with simulated performance of up to 6.3 CoreMark/MHz and a footprint of 0.067 mm2 TSMC’s 16nm CMOS process technology. The core supports the RISC-V RV32IMAC instruction set plus bit manipulation extensions.
SweRV Core™ EH2 by Western Digital
The SweRV Core EL2 is a second-generation SweRV core aimed at medium-performance embedded applications. It is a 32-bit, single issue with a 4-stage pipeline with simulated performance of 3.6 CoreMark/MHz and supporting the RISC-V RV32IMC instruction set.
SweRV Core™ EL2 by Western Digital
“We are excited to release support for Western Digital’s SweRV EH2 and EL2 cores made available through CHIPS Alliance,” noted Přemysl Václavík, Senior Director Open IP, Codasip. “The dual thread SweRV EH2 delivers outstanding embedded performance and the EL2 great silicon efficiency. Our SweRV Support Package will enable their rapid adoption in the market. We look forward to this solution helping to accelerate the RISC-V ecosystem.”
The SweRV Support Package, developed by Codasip in cooperation with Western Digital, provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based system-on-chip, integrated into one smart ready-to-use working environment. The Free version aimed at the educational market contains support for the software toolchain, open-source EDA tools, design flow integration, and a user forum. The Pro version additionally provides support for commercial EDA flows and professional customer support.
|
Codasip Hot IP
Related News
- Codasip Releases Support Package for Western Digital's First RISC-V SweRV Core
- Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip's RISC-V SweRV CORE Support Package Pro
- UltraSoC announces support for Western Digital RISC-V SweRV Core and OmniXtend cache-coherent interconnect
- Western Digital Extends Openness of PlatformIO and Enhances its RISC-V Portfolio to Accelerate Data-Centric Innovation
- SensiML Expands Platform Support to Include the RISC-V Architecture
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |