Efinix Announces Availability of Three RISC-V SoCs
SANTA CLARA, Calif.—June 2, 2020—Efinix®, an innovator in programmable product platforms and technology, today announced availability of a series of three software defined, SoCs based on the popular RISC-V® core.
The three designs have been optimized for Efinix’s Trion® family of FPGAs and provide a range of compute and I/O capabilities in devices from the T8 to the T120. To learn more, visit: www.efinixinc.com/riscv.
“RISC-V is a versatile and efficient embedded compute solution,” said Mark Oliver, senior director of marketing at Efinix. “Based on Charles Papon’s powerful and efficient VexRiscv design, our Trion® family of SoCs delivers pre-optimized RISC-V cores across the entire Trion FPGA product line from the cost optimized T8 right up to the T120. Users can now easily create and deploy entire SoCs including embedded compute, I/O and custom functionality.”
For ease of use, the SoCs are preconfigured with a RISC-V core, memory, a range of I/O and have interfaces for embedding user functions. In this way, designers can easily create entire systems that include embedded compute and user defined accelerators within the same FPGA.
“Since winning the RISC-V Soft CPU contest in 2018 and the Linux support addition, the VexRiscv core has been rising in popularity inside the open source community,” said Charles Papon, the designer of VexRiscv. “Optimizing the core into pre-defined configurations on the Trion family of FPGAs will give a much larger number of designers a turnkey and cost-effective way to access the power of the core in a broad variety of system designs.”
Efinix RISC-V SoCs come with a complete set of tools for compiling and debugging application code on the RISC-V core along with example applications and tutorials. They are compatible with the entire suite of Efinix development and evaluation boards and can be instantiated using the standard Efinity® tool flow.
About Efinix
Efinix, an innovator in programmable products, drives the future of edge AI computing with its Trion® FPGA silicon platform. At the Trion FPGA’s core is Efinix’s disruptive Quantum™ FPGA technology which delivers a 4X Power-Performance-Area advantage over traditional FPGA technologies. Trion FPGAs, offering 4K to 200K logic elements, have a small form-factor, low-power, and are priced for high-volume production. Our Efinity® Integrated Development Environment provides a complete FPGA design suite from RTL to bitstream. With their Power-Performance-Area advantage, Trion FPGAs address applications such as custom logic, compute acceleration, machine learning and deep learning. Through Efinity, our customers can seamlessly migrate FPGA or full system into Quantum ASIC for ultra-high-volume production.
|
Related News
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers
- GOWIN Semiconductor & Andes Technology Corp. Announce The First Ever RISC-V CPU and Subsystem Embedded 22nm SoC FPGA
- Microchip Adds Second Development Tool Offering for Designers Using Its Low-Power PolarFire RISC-V SoC FPGA for Embedded Vision Applications at the Edge
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |