Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud
Major reduction in turnaround time for next-generation chips achieved through collaboration
MOUNTAIN VIEW, Calif., June 15, 2020 -- Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with TSMC and Microsoft has delivered a ground-breaking, highly scalable timing signoff flow for use in the cloud. This extensive, multi-month collaboration among the three industry partners speeds up the path to signoff next-generation systems-on-chips (SoCs). The flow dramatically improves throughput using Synopsys PrimeTime® static timing analysis and StarRC™ parasitic extraction on the Microsoft Azure platform.
"With increasing design complexity due to advanced process technologies, larger library size, and higher number of operating conditions to analyze, turnaround time for the design signoff has become critical," said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. "Utilizing a cloud platform offers a great way to accelerate signoff significantly and will fundamentally influence silicon design. TSMC is the first foundry to collaborate with design ecosystem partners and cloud providers to enable design in the cloud. Working with Microsoft and Synopsys, our cloud alliance has demonstrated remarkable throughput improvement and scalability of timing signoff and offers a flexible, secure and efficient way for our mutual customers to accelerate time to market for their SoCs."
"At advanced nodes, reducing design time requires technology innovation across the infrastructure and toolchain due to high process complexity," said Mujtaba Hamid, head of product management, Silicon, Electronics and Gaming at Microsoft Azure. "This collaboration provides key insights into tradeoffs involved between cost and performance for these signoff iterations, thus helping the customers make effective decisions for the design of their silicon products."
On a multi-million gate design using the TSMC N5 process, PrimeTime static timing analysis and StarRC extraction, timing signoff was performed on Microsoft Azure's latest Edsv4-series compute instances. PrimeTime DMSA and StarRC multi-corner extraction scale-out saw significant throughput gains by massively parallelizing the runs over hundreds of machines. Additionally, scaling-in showed major cost savings by running multiple scenarios on a single machine.
"Working with leading-edge companies, we see the need for a high throughput of design tools and platforms to shorten time-to-market, whether they run the tools on-premise or in the cloud," said Jacob Avidan, senior vice president of Design Signoff in the Design Group at Synopsys. "With the industry-leading and TSMC-certified PrimeTime and StarRC solutions on Microsoft Azure, our customers can leverage the cloud to signoff their chips with significantly higher throughput while meeting their PPA targets with TSMC's latest advanced process technologies."
For more information, please download the new whitepaper titled "TSMC Timing Sign-Off in the Cloud with PrimeTime and StarRC," which is available immediately for customer download from TSMC-Online (https://online.tsmc.com/).
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud
- Cadence Collaborates with TSMC and Microsoft to Reduce Semiconductor Design Timing Signoff Schedules with the Cloud
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
- Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Advanced 4nm RF FinFET Process
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |